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| 型號： | FT2232HQ-TRAY |
| 廠商： | Future Technology Devices International Ltd |
| 元件分類： | 總線控制器 |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQCC64 |
| 封裝： | LEAD FREE, QFN-64 |
| 文件頁數(shù)： | 19/63頁 |
| 文件大?。?/td> | 1598K |
| 代理商： | FT2232HQ-TRAY |
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Copyright 2010 Future Technology Devices International Limited
26
Document No.: FT_000061
FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC
Datasheet Version 2.10
Clearance No.: FTDI#77
Name
Minimum
Typical
Minimum Units
Description
t1
16.67
ns
CLKOUT period
t2
7.5
8.33
ns
CLKOUT high period
t3
7.5
8.33
ns
CLKOUT low period
t4
1
7.15
ns
CLKOUT to RXF#
t5
1
7.15
ns
CLKOUT to read DATA valid
t6
1
7.15
ns
OE# to read DATA valid
t7
1
7.15
ns
CLKOUT to OE#
t8
11
ns
RD# setup time to CLKOUT (RD# low afterOE# low)
t9
0
ns
RD# hold time
t10
1
7.15
ns
CLKOUT TO TXE#
t11
11
ns
Write DATA setup time
t12
0
ns
Write DATA hold time
t13
11
ns
WR# setup time to CLKOUT (WR# low after TXE# low)
t14
0
ns
WR# hold time
Table 4.1 FT245 Synchronous FIFO Interface Signal Timings
This single channel mode uses a synchronous interface to get high data transfer speeds. The chip drives a
60 MHz CLKOUT clock for the external system to use.
Note that Asynchronous FIFO mode must be selected on both channels before selecting the Synchronous
FIFO mode in software.
4.4.1 FT245 Synchronous FIFO Read Operation
A read operation is started when the chip drives RXF# low. The external system can then drive OE# low
to turn around the data bus drivers before acknowledging the data with the RD# signal going low. The
first data byte is on the bus after OE# is low. The external system can burst the data out of the chip by
keeping RD# low or it can insert wait states in the RD# signal. If there is more data to be read it will
change on the clock following RD# sampled low. Once all the data has been consumed, the chip will drive
RXF# high. Any data that appears on the data bus, after RXF# is high, is invalid and should be ignored.
4.4.2 FT245 Synchronous FIFO Write Operation
A write operation can be started when TXE# is low. WR# is brought low when the data is valid. A burst
operation can be done on every clock providing TXE# is still low. The external system must monitor TXE#
and its own WR# to check that data has been accepted. Both TXE# and WR# must be low for data to be
accepted.
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