參數(shù)資料
型號(hào)： FT2232HL-TRAY
廠商： FTDI, Future Technology Devices International Ltd
文件頁數(shù)： 21/67頁
文件大?。?/td> 0K
描述： IC USB HS DUAL UART/FIFO 64-LQFP
標(biāo)準(zhǔn)包裝： 160
系列： USBmadeEZ-FIFO，F(xiàn)T-X，X-Chip
特點(diǎn)： USB 至 UART 和（或）FIFO、SPI、I2C、JTAG
通道數(shù)： 2，DUART
FIFO's： 4096 字節(jié)
規(guī)程： RS232，RS422，RS485
電源電壓： 3 V ~ 3.6 V
帶并行端口： 是
帶自動(dòng)流量控制功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP
包裝： 托盤
其它名稱： FT2232HL - TRAY
Copyright 2012 Future Technology Devices International Limited
28
Document No.: FT_000061
FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC
Version 2.21
Clearance No.: FTDI#77
Name
Minimum
Typical
Maximum Units
Description
t1
16.67
ns
CLKOUT period
t2
7.5
8.33
9.17
ns
CLKOUT high period
t3
7.5
8.33
9.17
ns
CLKOUT low period
t4
1
7.15
ns
CLKOUT to RXF#
t5
1
7.15
ns
CLKOUT to read DATA valid
t6
1
7.15
ns
OE# to read DATA valid
t7
8
16.67
ns
OE# setup time
T8
0
ns
OE# hold time
T9
8
16.67
ns
RD# setup time to CLKOUT (RD# low afterOE# low)
T10
0
ns
RD# hold time
t11
1
7.15
ns
CLKOUT TO TXE#
t12
8
16.67
ns
Write DATA setup time
t13
0
ns
Write DATA hold time
t14
8
16.67
ns
WR# setup time to CLKOUT (WR# low after TXE# low)
t15
0
ns
WR# hold time
Table 4.1 FT245 Synchronous FIFO Interface Signal Timings
This single channel mode uses a synchronous interface to get high data transfer speeds. The chip drives a
60 MHz CLKOUT clock for the external system to use.
Note that Asynchronous FIFO mode must be selected on both channels before selecting the Synchronous
FIFO mode in software.
4.4.1 FT245 Synchronous FIFO Read Operation
A read operation is started when the chip drives RXF# low. The external system can then drive OE# low
to turn around the data bus drivers before acknowledging the data with the RD# signal going low. The
first data byte is on the bus after OE# is low. The external system can burst the data out of the chip by
keeping RD# low or it can insert wait states in the RD# signal. If there is more data to be read it will
change on the clock following RD# sampled low. Once all the data has been consumed, the chip will drive
RXF# high. Any data that appears on the data bus, after RXF# is high, is invalid and should be ignored.
4.4.2 FT245 Synchronous FIFO Write Operation
A write operation can be started when TXE# is low. WR# is brought low when the data is valid. A burst
operation can be done on every clock providing TXE# is still low. The external system must monitor TXE#
and its own WR# to check that data has been accepted. Both TXE# and WR# must be low for data to be
accepted.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
FT2232HMINIMODULE 制造商:Future Technology Devices International (FTDI Chip) 功能描述:USB Hi-Speed FT2232H Evaluation Module 制造商:Future Technology Devices International (FTDI Chip) 功能描述:USB to serial/FIFO development module
FT2232H-MINI-MODULE 制造商:Future Technology Devices International (FTDI Chip) 功能描述:IC,EVALUATION MODULE;FT2232H;USB HI-SPEED
FT2232HQ 制造商:Future Technology Devices International (FTDI Chip) 功能描述:USB Hi-Speed to Dual Channel Serial UART/FIFO/JTAG/SPI/I2C IC - QFN-64
FT2232HQ_MINI_ MODULE 功能描述:界面開發(fā)工具 USB Hi-Speed FT2232H Evaluation Module RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
FT2232HQ-4000 制造商:FTDI 制造商全稱:FTDI 功能描述:DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC
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