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參數(shù)資料
| 型號： | FSA2269UMX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 4/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SWITCH DUAL SPDT 10UMLP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 功能： | 開關(guān) |
| 電路： | 2 x SPDT |
| 導(dǎo)通狀態(tài)電阻： | 300 毫歐 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 1.65 V ~ 4.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-UFQFN |
| 供應(yīng)商設(shè)備封裝： | 10-UMLP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1218 (CN2011-ZH PDF) |
| 其它名稱： | FSA2269UMXDKR |
2007 Fairchild Semiconductor Corporation
www.f airchildsemi.com
FSA2269 / FSA2269TS Rev. 1.1.5
12
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Physical Dimensions (Continued)
Figure 21.
10-Lead, Quad Ultrathin Molded Leadless Package (UMLP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the t
erms of Fairchild’s worldwide terms and conditions,
specifically the w arranty therein, w hich covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
A
B
C
SEATING
PLANE
DETAIL A
PIN#1 IDENT
RECOMMENDED
LAND PATTERN
NOTES:
A. PACKAGE DOES NOT CONFORM TO
ANY JEDEC STANDARD.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
D. LAND PATTERN RECOMMENDATION IS
BASED ON FSC DESIGN ONLY.
E. DRAWING FILENAME: MKT-UMLP10Arev5.
F. FAIRCHILD SEMICONDUCTOR.
TOP VIEW
BOTTOM VIEW
0.10 C
0.08 C
0.10 C
2X
SIDE VIEW
0.10 C
0.05
0.00
3
6
1
0.10 C A B
0.05 C
0.55 MAX.
10
1.40
1.80
0.40
0.15
0.25
(10X)
0.35
0.45
(9X)
1.70
2.10
0.40
0.663
0.563
(9X)
0.225
(10X)
1
(0.15)
0.55
0.45
DETAIL A
SCALE : 2X
1.85
1.45
0.55
0.40
0.225
(10X)
9X
0.45
PIN#1 IDENT
OPTIONAL MINIMIAL
TOE LAND PATTERN
SCALE : 2X
LEAD
OPTION 1
SCALE : 2X
LEAD
OPTION 2
PACKAGE
EDGE
45°
0.25
0.15
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