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參數(shù)資料
| 型號： | FS7145-02G-XTP |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 15/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN PLL PROG 16SSOP |
| 標準包裝： | 1,500 |
| 類型： | 時鐘/頻率合成器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | CMOS，PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 300MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 帶卷 (TR) |
FS7140, FS7145
http://onsemi.com
7
Figure 2. Post Divider
The moduli of the individual dividers are denoted as NP1,
NP2 and NP3, and together they make up the array modulus
NPX.
NPX = NP1 x NP2 x NP3
The post divider performs several useful functions. First,
it allows the VCO to be operated in a narrower range of
speeds compared to the variety of output clock speeds that
the device is required to generate. Second, the extra integer
in the denominator permits more flexibility in the
programming of the loop for many applications where
frequencies must be achieved exactly.
Note that a nominal 50/50 duty factor is always preserved
(even for selections which have an odd modulus).
See Table 12 for additional information.
Crystal Oscillator
The FS7140 is equipped with a Piercetype crystal
oscillator. The crystal is operated in parallel resonant mode.
Internal load capacitance is provided for the crystal. While
a recommended load capacitance for the crystal is specified,
crystals for other standard load capacitances may be used if
great precision of the reference frequency (100 ppm or less)
is not required.
Reference Divider Source MUX
The source of frequency for the reference divider can be
chosen to be the device crystal oscillator or the REF pin by
the REFDSRC bit.
When not using the crystal oscillator, it is preferred to
connect XIN to VSS. Do not connect to XOUT.
When not using the REF input, it is preferred to leave it
floating or connected to VDD.
Feedback Divider Source MUX
The source of frequency for the feedback divider may be
selected to be either the output of the post divider or the
output of the VCO by the FBKDSRC bit.
Ordinarily, for frequency synthesis, the output of the VCO
is used. Use the output of the post divider only where a
deterministic phase relationship between the output clock
and reference clock are desired (linelocked mode, for
example).
Device Shutdown
Two bits are provided to effect shutdown of the device if
desired, when it is not active. SHUT1 disables most
externally observable device functions. SHUT2 reduces
device quiescent current to absolute minimum values.
Normally, both bits should be set or cleared together.
Serial communications capability is not disabled by either
SHUT1 or SHUT2.
Differential Output Stage
The differential output stage supports both CMOS and
pseudoECL (PECL) signals. The desired output interface
is chosen via the programming registers.
If a PECL interface is used, the transmission line is usually
terminated using a Thévenin termination. The output stage
can only sink current in the PECL mode, and the amount of
sink current is set by a programming resistor on the
LOCK/IPRG pin. The ratio of output sink current to IPRG
current is 13:1. Source current for the CLKx pins is provided
by the pullup resistors that are part of the Thévenin
termination.
Example
Assume that it is desired to connect a PECLtype fanout
buffer right next to the FS7140.
Further assume:
VDD = 3.3 V
Desired VHI = 2.4 V
Desired VLO = 1.6 V
Equivalent RLOAD = 75 ohms
Then:
R1 (from CLKP and CLKN output to VDD) =
RLOAD * VDD / VHI =
75 * 3.3 / 2.4 =
103 ohms
R2 (from CLKP and CLKN output to GND) =
RLOAD * VDD / (VDD VHI) =
75 * 3.3 / (3.3 2.4) =
275 ohms
Rprgm (from VDD to IPRG pin) =
26 * (VDD * RLOAD) / (VHI VLO) / 3 =
26 * (3.3 * 75) / (2.4 1.6) / 3 =
2.68 Kohms
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