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參數(shù)資料
| 型號： | FS7145-02G-XTP |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN PLL PROG 16SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 時鐘/頻率合成器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | CMOS，PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 300MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 帶卷 (TR) |
FS7140, FS7145
http://onsemi.com
6
Table 6. SERIAL INTERFACE TIMING SPECIFICATIONS (Note 3)
Parameter
Symbol
Conditions/Description
Fast Mode
Units
Min
Max
Clock frequency
fSCL
SCL
0
400
kHz
Bus free time between STOP and START
tBUF
1300
ns
Setup time, START (repeated)
Tsu:STA
600
ns
Hold time, START
thd:STA
600
ns
Setup time, data input
Tsu:DAT
SDA
100
ns
Hold time, data input
thd:DAT
SDA
0
ns
Output data valid from clock
tAA
900
ns
Rise time, data and clock
tR
SDA, SCL
300
ns
Fall time, data and clock
tF
SDA, SCL
300
ns
High time, clock
tHI
SCL
600
ns
Low time, clock
tLO
SCL
1300
ns
Setup time, STOP
tsu:STO
600
ns
3. Unless otherwise stated, VDD = 3.3 V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted
with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization
data are ± 3s from typical.
FUNCTIONAL BLOCK DIAGRAM
Phase Locked Loop (PLL)
The PLL is a standard phase and frequencylocked loop
architecture. The PLL consists of a reference divider, a
phasefrequency detector (PFD), a charge pump, an internal
loop filter, a voltagecontrolled oscillator (VCO), a
feedback divider, and a post divider.
The reference frequency (generated by either the
onboard crystal oscillator or an external frequency source),
is first reduced by the reference divider. The integer value
that the frequency is divided by is called the modulus and is
denoted as NR for the reference divider. This divided
reference is then fed into the PFD.
The VCO frequency is fed back to the PFD through the
feedback divider (the modulus is denoted by NF).
The PFD will drive the VCO up or down in frequency until
the divided reference frequency and the divided VCO
frequency appearing at the inputs of the PFD are equal. The
input/output relationship between the reference frequency
and the VCO frequency is then:
fVCO
NF
+
fREF
NR
This basic PLL equation can be rewritten as
fVCO + fREF
NF
NR
A post divider (actually a series combination of three post
dividers) follows the PLL and the final equation for device
output frequency is:
fCLK + fREF
NF
NR
1
NPx
Reference Divider
The reference divider is designed for low phase jitter. The
divider accepts the output of either the crystal oscillator
circuit or an external reference frequency. The reference
divider is a 12 bit divider, and can be programmed for any
modulus from 1 to 4095 (divide by 1 not available on date
codes prior to 0108).
Feedback Divider
The feedback divider is based on a dualmodulus divider
(also called dualmodulus prescaler) technique. It permits
division by any integer value between 12 and 16383. Simply
program the FBKDIV register with the binary equivalent of
the desired modulus. Selected moduli below 12 are also
permitted. Moduli of: 4, 5, 8, 9, and 10 are also allowed (4
and 5 are not available on date codes prior to 0108).
Post Divider
The post divider consists of three individually
programmable dividers, as shown in Figure 2.
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