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參數資料
| 型號： | FS6209-01 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | CAP 0.022UF 25V 10% X7R SMD-0603 TR-7-PA 5K/REEL |
| 中文描述： | 雙鎖相環(huán)壓控時鐘發(fā)生器IC |
| 文件頁數： | 4/6頁 |
| 文件大小： | 113K |
| 代理商： | FS6209-01 |
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February 1999
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Table 5: DC Electrical Specifications
Unless otherwise stated, V
= 3.3V ± 10%, no load on any output, and ambient temperature range T
= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are
±
3
σ
from typical. Negative currents indicate current flows out of the device.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
Overall
Supply Current, Dynamic, with Loaded
Outputs
I
DD
f
XTAL
= 13.5MHz; C
L
= 10pF
20
mA
Voltage Controlled Crystal Oscillator
Crystal Resonator Frequency
f
XTAL
Fundamental Mode
As seen by a crystal connected to XIN and
XOUT (@ V
XTUNE
= 1.65V)
AT cut
f
XTAL
= 13.5MHz; C
L
= 20pF; C
MOT
= 25fF
Note: positive
-
F for positive
-
V
R
XTAL
=20 ohm; C
L
= 20pF
5.
13.5
18
MHz
Crystal Loading Capacitance
C
L(xtal)
20
pF
Crystal Resonator Motional Capacitance
VCXO Tuning Range
VCXO Tuning Characteristic
C
1(xtal)
25
300
100
fF
ppm
ppm/V
Crystal Drive Level
200
uW
Clock Outputs (CLKA, CLKB, CLKC)
High-Level Output Source Current *
Low-Level Output Sink Current *
I
OH
I
OL
z
OH
z
OL
I
OSH
I
OSL
V
O
= 2.0V
V
O
= 0.4V
V
O
= 0.1V
DD
; output driving high
V
O
= 0.1V
DD
; output driving low
V
O
= 0V; shorted for 30s, max.
V
O
= 3.3V; shorted for 30s, max.
40
17
25
25
55
55
mA
mA
Output Impedance *
Short Circuit Source Current *
Short Circuit Sink Current *
mA
mA
Table 6: AC Timing Specifications
Unless otherwise stated, V
= 3.3V ± 10%, no load on any output, and ambient temperature range T
= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are
±
3
σ
from typical.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
CLOCK
(MHz)
MIN.
TYP.
MAX.
UNITS
Clock Outputs (CLKx)
Duty Cycle *
t
hi
/ t
clk
; Measured at V
DD
/2
From rising edge to next rising edge at
V
DD
/2, C
L
= 10pF
From 0-500
μ
s at V
DD
/2, C
L
= 10pF
compared to ideal clock source
V
DD
= 3.3V; V
O
= 0.3V to 3.0V; C
L
= 10pF
V
DD
= 3.3V; V
O
= 3.0V to 0.3V; C
L
= 10pF
(unless otherwise noted in Frequency Table)
From power valid
From VCXO stable
43
57
%
Jitter, Absolute Period (pk-pk) *
t
j(
P)
300
ps
Jitter, RMS Long Term (
σ
y
(
τ
)) *
t
j(LT)
150
ps
Rise Time *
Fall Time *
Output Frequency Synthesis Error
VCXO Stabilization Time *
PLL Stabilization Time *
t
r
t
f
1
1
ns
ns
ppm
ms
us
0
t
VCXOSTB
t
PLLSTB
10
500
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