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參數(shù)資料
| 型號： | FS6131-01G |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 27 MHz, PDSO16 |
| 封裝： | 0.150 INCH, GREEN, SOP-16 |
| 文件頁數(shù)： | 21/40頁 |
| 文件大小： | 746K |
| 代理商： | FS6131-01G |
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28
AMI Semiconductor - Rev. 2.0, Jun. 05
www.amis.com
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
10.3.3 Example: Line-Locked Mode
Selecting the line-locked/genlock option in the Device Mode block changes the program default settings. The Reference Source changes to the
REF pin input, and a block appears to permit entry of the REF input frequency in MHz. A Desired Multiple block allows entry of the reference
frequency multiplying factor used to generate the output frequency.
Exercise: Change the ref pin frequency to 0.0315MHz, and alter the desired multiple to 800. Change the loop filter block to external, but leave
the values for C1 and R alone.
Click on Calculate Solutions. The program takes into account all of the current screen settings and calculates all possible combinations of
reference, feedback and post divider values that will generate an output frequency from the input frequency (31.5kHz) multiplied by the desired
multiple of 800.
A box will appear: "No solutions were found! Do you want to retry calculations with the check loop stability option turned off?" Choose Yes.
Another box will momentarily appear: "Calculating Solutions: Press cancel to stop with the solutions calculated so far." A number in the box will
increment for every unique solution that is found. This example will create eight unique solutions, which are then displayed in a window in the
lower right portion of the program screen.
For best results, try to keep the PostDiv value multiplied by the FbkDiv value from getting larger than 5000 while running the VCO as much above
70MHz as possible. If a tradeoff must be made, it is better to run the VCO faster and allow the divider values to get large. Solution #4 provides a
PostDiv value of 800 and a FbkDiv value of 4 for a combined value of 3200. The VCO is running at about 100MHz.
Click on Solution #4 to highlight the row, then click on Suggest in the Loop Filter box to have the program choose loop filter values. Suggested
values for an external loop filter are 4700pF and 47k
W.
Now reselect the Check Loop Stability box to turn this feature on. Clicking on Calculate Solutions regenerates the same solutions provided
earlier, only this time the new loop filter values were used.
Figure 21: Line-Locked Screen
Clicking on Solution #4 highlights the row, and clicking on Disp/Save Register Values provides a window with the final values of key settings. A
click on OK then displays a second window containing register information per the register map. If the solutions are to be saved to a file, two
formats are available: a text format for viewing and a data format for loading into the FS6131.
Note: As an update to this data sheet, the FS6131 hardware is no longer available from AMIS.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| FS6131-01G-XTD | 功能描述:時鐘發(fā)生器及支持產品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01G-XTP | 功能描述:時鐘發(fā)生器及支持產品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01I-XTD | 功能描述:時鐘發(fā)生器及支持產品 I2C PROG PLL CLK (IND) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01I-XTP | 功能描述:時鐘發(fā)生器及支持產品 I2C PROG PLL CLK IND RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6186-16/24 | 制造商:Schaffner 功能描述: |
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