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參數(shù)資料
| 型號： | FS6131-01G |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 27 MHz, PDSO16 |
| 封裝： | 0.150 INCH, GREEN, SOP-16 |
| 文件頁數(shù)： | 2/40頁 |
| 文件大小： | 746K |
| 代理商： | FS6131-01G |
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AMI Semiconductor - Rev. 2.0, Jun. 05
www.amis.com
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
4.5 Crystal Loop
The crystal loop is designed to attenuate the jitter on a highly jittered, low-Q, low frequency reference. The crystal loop can also maintain a
constant frequency output into the main loop if the low frequency reference is intermittent.
The crystal loop consists of a voltage-controllable crystal oscillator (VCXO), a divider, a PFD, and a charge pump that tunes the VCXO to a
frequency reference. The frequency reference is phase-locked to the divided frequency of an external, high-Q, jitter-free crystal, thereby locking
the VCXO to the reference frequency. The VCXO can continue to run off the crystal even if the frequency reference becomes intermittent.
4.5.1 Locking to an External Frequency Source
When the crystal loop is synchronized to an external frequency source, the FS6131 can monitor the crystal loop and detect if the loop unlocks
from the external source. The crystal loop tries to drive to zero frequency if the external source is dropped, and sets a lock status error flag.
The crystal loop can also detect if the VCXO has dropped out of the fine tune range, requiring a change to the coarse tune. The lock status also
latches the direction the loop went out of range (high or low) when the loop became unlocked.
4.5.1.1 Crystal Loop Lock Status Flag
To enable this mode, clear the STAT[1] and STAT[0] bits to zero. If the CMOS bit is set to one, the LOCK/IPRG pin will be low if the crystal loop
becomes unlocked. The flag is always available under software control by reading back the STAT[1] bit, which is overwritten with the status flag
(low = unlocked) in this mode (see Table 6).
4.5.1.2 Out-Of-Range High/Low
The direction the loop has gone out-of-range can be determined by clearing STAT[1] to zero and setting STAT[0] bit to one. If the CMOS bit is set
to one, the LOCK/IPRG pin will go high if the crystal loop went out of range high. If the pin goes to a logic-low, the loop went out of range low.
The out-of-range information is also available under software control by reading back the STAT[1] bit, which is overwritten by the flag (high = out-
of-range high, low = out-of-range low) in this mode. The bit is set or cleared only if the crystal loop loses lock (see Table 6).
4.5.1.3 Crystal Loop Disable
The crystal loop is disabled by setting the XLPDEN bit to a logic-high (1). The bit disables the charge pump circuit in the loop.
Setting the XLPDEN bit low (0) permits the crystal loop to operate as a control loop.
4.6 Connecting the FS6131 to an External Reference Frequency
If a crystal oscillator is not used, tie XIN to ground and shut down the crystal oscillator by setting XLROM[2:0]=1.
The REF and FBK pins do not have pull-up or pull-down current, but do have a small amount of hysteresis to reduce the possibility of extra edges.
Signals may be AC-coupled into these inputs with an external DC-bias circuit to generate a DC-bias of 2.5V. Any reference or feedback signal
should be square for best results, and the signals should be rail-to-rail. Unused inputs should be grounded to avoid unwanted signal injection.
4.7 Differential Output Stage
The differential output stage supports both CMOS and pseudo-ECL (PECL) signals. The desired output interface is chosen via the program
registers (see Table 4).
If a PECL interface is used, the transmission line is usually terminated using a Thévenin termination. The output stage can only sink current in the
PECL mode, and the amount of sink current is set by a programming resistor on the LOCK/IPRG pin. The ratio of IPRG current to output drive
current is shown in Figure 12. Source current is provided by the pull-up resistor that is part of the Thévenin termination.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FS6131-01G-XTD | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01G-XTP | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01I-XTD | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK (IND) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01I-XTP | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK IND RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6186-16/24 | 制造商:Schaffner 功能描述: |
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