參數(shù)資料
型號(hào)： FS6131-01
元件分類： PLL合成/DDS/VCOs
英文描述： PLL FREQUENCY SYNTHESIZER, 27 MHz, PDSO16
封裝： 0.150 INCH, SOP-16
文件頁數(shù)： 4/40頁
文件大?。?/td> 746K
代理商： FS6131-01
12
AMI Semiconductor - Rev. 2.0, Jun. 05
www.amis.com
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
Each data transfer is initiated by a START condition and terminated with a STOP condition. The number of data bytes transferred between START
and STOP conditions is determined by the master device, and can continue indefinitely. However, data that is overwritten to the device after the
first eight bytes will overflow into the first register, then the second, and so on, in a first-in, first-overwritten fashion.
5.1.5 Acknowledge
When addressed, the receiving device is required to generate an acknowledge after each byte is received. The master device must generate an
extra clock pulse to coincide with the acknowledge bit. The acknowledging device must pull the SDA line low during the high period of the master
acknowledge clock pulse. Setup and hold times must be taken into account.
The master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been read (clocked) out of the
slave. In this case, the slave must leave the SDA line high to enable the master to generate a STOP condition.
5.2 I
2C-bus Operation
All programmable registers can be accessed randomly or sequentially via this bi-directional two wire digital interface. The crystal oscillator does
not have to run for communication to occur.
The device accepts the following I
2C-bus commands:
5.2.1 Slave Address
After generating a START condition, the bus master broadcasts a seven-bit slave address followed by a R/W bit. The address of the device is:
A6
A5
A4
A3
A2
A1
A0
1
0
1
X
0
where X is controlled by the logic level at the ADDR pin. The variable ADDR bit allows two different FS6131 devices to exist on the same bus.
Note that every device on an I
2C-bus must have a unique address to avoid bus conflicts. The default address sets A2 to 0 via the pull-down on
the ADDR pin.
5.2.2 Random Register Write Procedure
Random write operations allow the master to directly write to any register. To initiate a write procedure, the R/W bit that is transmitted after the
seven-bit device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the slave device
acknowledges its device address. The register address is written into the slave's address pointer. Following an acknowledge by the slave, the
master is allowed to write eight bits of data into the addressed register. A final acknowledge is returned by the device, and the master generates
a STOP condition.
If either a STOP or a repeated START condition occurs during a register write, the data that has been transferred is ignored.
5.2.3 Random Register Read Procedure
Random read operations allow the master to directly read from any register. To perform a read procedure, the R/W bit that is transmitted after the
seven-bit address is a logic-low, as in the register write procedure. This indicates to the addressed slave device that a register address will follow
after the slave device acknowledges its device address. The register address is then written into the slave's address pointer.
Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure,
but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to
the slave that data will be read. The slave will acknowledge the device address, and then transmits the eight-bit word. The master does not
acknowledge the transfer but does generate a STOP condition.
5.2.4 Sequential Register Write Procedure
Sequential write operations allow the master to write to each register in order. The register pointer is automatically incremented after each write.
This procedure is more efficient than the random register write if several registers must be written.
To initiate a write procedure, the R/W bit that is transmitted after the seven-bit device address is a logic-low. This indicates to the addressed slave
device that a register address will follow after the slave device acknowledges its device address. The register address is written into the slave's
相關(guān)PDF資料
PDF描述
FS6131-01 PLL FREQUENCY SYNTHESIZER, 27 MHz, PDSO16
FS6S0965R-YDTU 36 A SWITCHING REGULATOR, 150 kHz SWITCHING FREQ-MAX, PZFM5
FS6S0965R-TU 36 A SWITCHING REGULATOR, 150 kHz SWITCHING FREQ-MAX, PSFM5
FS6S1265RE-YDTU 48 A SWITCHING REGULATOR, 150 kHz SWITCHING FREQ-MAX, PZFM5
FS6S1265RB-YDTU 48 A SWITCHING REGULATOR, 150 kHz SWITCHING FREQ-MAX, PZFM5
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
FS6131-01G 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Programmable Line Lock Clock Generator IC
FS6131-01G-XTD 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
FS6131-01G-XTP 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
FS6131-01I-XTD 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK (IND) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
FS6131-01I-XTP 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK IND RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
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