參數(shù)資料
型號(hào)： FS6131-01
元件分類： PLL合成/DDS/VCOs
英文描述： PLL FREQUENCY SYNTHESIZER, 27 MHz, PDSO16
封裝： 0.150 INCH, SOP-16
文件頁(yè)數(shù)： 28/40頁(yè)
文件大?。?/td> 746K
代理商： FS6131-01
34
AMI Semiconductor - Rev. 2.0, Jun. 05
www.amis.com
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
13.0 Device Application: Line-Locked Clock Generation
Line-locked clock generation, as used here, refers to the process of synthesizing a clock frequency that is some integer multiple of the horizontal
line frequency in a graphics system. The FS6131 is easily configured to perform that function, as shown in Figure 26.
A line reference signal (fHSYNC) is applied to the REF input for direct application to the main loop PFD. The feedback divider (NF) is programmed for
the desired number of output clocks per line.
The source for the feedback divider is selected to be the output of the post divider (NPx) so that the edges of the output clock maintain a consistent
phase alignment with the line reference signal. The modulus of the post divider should be selected to maintain a VCO frequency that is comfortably
within the operating range noted in Table 15.
13.1 Example Calculation
A Visual BASIC program is available to completely program the FS6131 based on the given parameters.
Suppose that we wish to reconstruct the pixel clock from a VGA source. This is a typical requirement of an LCD projection panel application.
First, establish the total number of pixel clocks desired between horizontal sync (HSYNC) pulses. The number of pixel clocks is known as the
horizontal total, and the feedback divider is programmed to that value. In this example, choose the horizontal total to be 800.
Next, establish the frequency of the HSYNC pulses (fHSYNC) on the line reference signal for the video mode. In this case, let fHSYNC=31.5kHz. The
output clock frequency fCLK is calculated to be:
MHz
175
.
25
800
kHz
5
.
31
=
=
=
F
HSYNC
CLK
N
f
Reference
HSYNC
FS6131
VCXO
Divider
(optional)
CRYSTAL LOOP
MAIN LOOP
VCXO
XOUT
XIN
Control
ROM
XTUNE
Reference
Divider
(N
R)
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
REF
FBK
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
Feedback
Divider (N
F)
Internal
Loop
Filter
EXTLF
I2C
Interface
SCL
SDA
ADDR
Registers
POST3[1:0],
POST2[1:0],
POST1[1:0]
REFDIV[11:0]
FBKDIV[14:0]
EXTLF
PDREF
PDFBK
VCOSPD,
OSCTYPE
LFTC
MLCP[1:0]
XLCP[1:0]
XLROM[2:0]
XLPDEN,
XLSWAP
REFDSRC
XCT[3:0],
XLVTEN
(f
REF)
(f
VCO)
LOCK/
IPRG
Post
Divider
(N
Px)
Voltage
Controlled
Oscillator
Lock
Detect
CMOS
(optional)
STAT[1:0]
OM[1:0]
Clock
Gobbler
GBL
(optional)
FBKDSRC[1:0]
CMOS/PECL
Output
CLKN
(f
CLK)
CLKP
R
LF
C
LF
R
IPRG
C
LP
Figure 26: Block Diagram: Line-Locked Clock Generation
相關(guān)PDF資料
PDF描述
FS6131-01 PLL FREQUENCY SYNTHESIZER, 27 MHz, PDSO16
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
FS6131-01G 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Programmable Line Lock Clock Generator IC
FS6131-01G-XTD 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
FS6131-01G-XTP 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
FS6131-01I-XTD 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK (IND) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
FS6131-01I-XTP 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK IND RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
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