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參數(shù)資料
| 型號： | FPD85308 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Panel Timing Controller |
| 中文描述： | 小組定時控制器 |
| 文件頁數(shù)： | 22/31頁 |
| 文件大?。?/td> | 474K |
| 代理商： | FPD85308 |
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Functional Description
(Continued)
DS101356-10
Note 21:
RSTZ transition Low-to-High occurs at the completion of the RPLLS delay or later as shown above.
Note 22:
All outputs* forced low in default timing of FPD85308 during power-up delay time.
Note 23:
All outputs
**
forced low in continuous download (every two frame) mode.
Note 24:
All outputs
***
generate the signal for default values in FPD85308 and unknown values when use the EEPROM values during power-up delay time. Then
NS recommend to use the continuous download mode.
Note 25:
EEPROM download occurs at first detected vertical blanking period.
Note 26:
Active outputs depends on INPUT FORMAT register bits [5:6].
INPUT
FORMAT
[5:6]
00
01
10
11
VSYNC# at which
outputs go active
Second VSYNC
Third VSYNC
Fourth VSYNC
Fifth VSYNC
Note 27:
When configured in ENAB Only Mode (EOM), VSYNC signals are unused except for timing EEPROM DownLoad Sequences. When configured with
default values in Fixed Vertical mode, the VSYNC signal is generated any time ENAB remains low for more than 2 horizontal periods.
During Power Up, before Reset has propagated, the EEPROM may receive spurious addressing that initiates a down load sequence, but the output data is often
not captured for lack of timing alignment with VSYNC. In the case where EEPROM data is not captured during the initial (automatic) Reset or Power Up DownLoad
sequence, Timing Controller outputs are indeterminate until the EEPROM data is successfully loaded, which always begins and is executed at the next VSYNC valid
(low) cycle.
Note 28:
During Power Up sequences, false RSTZ signals are possible due to instability of the power supply level, typically within the 10 ms of operation. To avoid
this situation, implementation of the circuit in Figure 19 or other functional equivalent, is recommended, (Figure 19).
FIGURE 18. Power-up Sequence (INPUT FORMAT[6:5] = “01”)
F
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| FPD87310 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Universal Interface XGA Panel Timing Controller with RSDS⑩ (Reduced Swing Differential Signaling) and FPD-Link |
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