參數(shù)資料
型號(hào): FPD85308
廠商: National Semiconductor Corporation
英文描述: Panel Timing Controller
中文描述: 小組定時(shí)控制器
文件頁數(shù): 14/31頁
文件大小: 474K
代理商: FPD85308
Functional Description
(Continued)
TABLE 2. FPD85308 Programmable Register Definition
(Continued)
Control
Registers
Vertical
Backporch (11
bits)
Horizontal
Backporch (11
bits)
General
Purpose Output
Registers
(9 sets)
EEPROM
Address
DA, D9
The control registers provide mode setting information to the input and output interfaces.
# of HSYNCS from VSYNC falling edge until start of video
D8, D7
# of 65 MHz clocks after the falling edge of HSYNC until start of video
See
Table 3
EEPROM
Memory
Map
The GPO registers provide complete control over placement of control edges/strobes within the
data frame. The GPO timing registers (Vertical Start, Vertical Duration, Horizontal Start, and
Horizontal Duration) define the control timing relative to the internal line and pixel counters. The
line counter corresponds to the line being displayed. The pixel counter corresponds to the pixel
output each line. The Control Register provides polarity selection and/or generation of a line to
line frame-to-frame alternating signal (REV). Each General Purpose Output can be uniquely
configured. See the GPO programming examples for details.
- GPO [0] provides for the data inversion function enabled by bit 3 of the Output Format Control
Register
- GPO [8] provides programmable data and clock blanking
Line # at which GPO [X] control generation begins
Vertical Start
(11 bits)
Vertical
Duration
(11 bits)
Horizontal Start
(10 bits)
# lines GPO [X] control generation continues
(if “0”, Vertical component is always on)
Internal count (pixel counter) at which GPO [X] goes active to be triggered on rising edge of the
OCLK
Note: If control register [1] = “1”, start position will be moved by 1 pixel clock
# Pixel Clocks/2 GPO [X] is active after Horizontal Start
(if “0”, Horizontal component is always on)
Horizontal
Duration
(11 bits)
F
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