參數(shù)資料
型號: FMS988AKAC100
英文描述: Signal Conditioner
中文描述: 信號調(diào)理
文件頁數(shù): 24/29頁
文件大?。?/td> 481K
代理商: FMS988AKAC100
PRODUCT SPECIFICATION
FMS9875
24
REV. 1.2.15 1/14/02
Clock Input
t
JPP
Peak-to-peak PLL Jitter
MHz
31.5
49.5
78.75
108
135
MHz
31.5
49.5
78.75
108
135
MHz
31.5
49.5
MHz
31.5
49.5
25
°
C
C
ps
6000
3117
1493
892
750
t
JRMS
RMS Jitter
25
°
C
C
ps
873
488
245
148
122
t
J2PP
Peak-to-peak jitter with
subdivide ratio equal
to 2.
25
°
C
C
ps
1600
1700
t
J2RMS
RMS jitter with subdivide
ratio equal to 2.
25
°
C
C
ps
330
203
Parameter
Temp.
Test
Rank
Min.
Typ.
Max.
Unit
Figure 21. Pixel Clock Peak-to-Peak Jitter
Figure 22. Pixel Clock RMS Jitter
6000
5000
4000
3000
2000
1000
10000
9000
8000
7000
00
20
40
60
80
VCO Frequency, MHz
P
100
120
140
160
200
400
600
800
1000
1200
1400
0
VCO Frequency, MHz
R
0
20
40
60
80
100
120
140
160
Figure 23. Pixel Clock % RMS Jitter
1%
2%
3%
4%
5%
0
VCO Frequency, MHz
R
0
20
40
60
80
100
120
140
160
PLL Performance Characteristics
Notes
1. In Figures 21-23, the dashed curve is with subdivide ratio = 2.
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