參數(shù)資料
型號(hào)： FMS988AKAC100
英文描述： Signal Conditioner
中文描述： 信號(hào)調(diào)理
文件頁(yè)數(shù)： 13/29頁(yè)
文件大?。?/td> 481K
代理商： FMS988AKAC100
FMS9875
PRODUCT SPECIFICATION
REV. 1.2.15 1/14/02
13
Figure 7. Output Timing
PHASE
N
t
SKEW
P0
D0
PXCK/XCK
SC
HSIN
K
GBR
IN
/YP
B
P
RIN
DCK
HSOUT
DCK
D[7..0]
Figures 8 through 12 depict data output timing relative to the
sampling clock and inputs for all modes. Timing is referenced
to the leading edge of HSIN when the first sample is taken at
the rising edge of SCK. Register bit OUTPHASE, determines
if odd or even samples are directed to the data ports.
Note the timing of the HSOUT waveform:
1.
HSOUT is always active HIGH.
2.
Leading edge of HSOUT is aligned to the leading or
trailing edge (selected by the HSPOL register bit) of
HSIN delayed by 5 to 5.5 pixels
3.
Leading edge is aligned with DCK.
4.
Trailing edge is linked to HSIN.
5.
If HSIN does not terminate before mid-line, HSOUT is
forced low. A 50% duty cycle indicates that HSPOL is
incorrectly set.
HS is the internal sync pulse generated from HSIN. SCK is
the internal A/D converter sampling clock.
Pixel sampling is referenced to the rising edge of HSIN.
Data outputs are delayed by 5 to 5.5 pixels. To allow for
clamping, start-of-active-video (SAV) can begin any time
after the falling edge of HSIN. End-of-active-video (EAV)
follows SAV any time before the next HSIN pulse.
Figure 8. GBR Mode
GBR
IN
HSIN
PXCK
HS
SCK
DCK
DGBR
7-0
HSOUT
P6
P0
P1
P2
P3
P4
P5
D6
D0
D1
D2
D3
D4
D5
P7
D7
5 PIXEL DELAY
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