參數(shù)資料
型號: FMS9875KGC140X
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: ADC
英文描述: 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP100
封裝: MQFP-100
文件頁數(shù): 18/31頁
文件大?。?/td> 517K
代理商: FMS9875KGC140X
FMS9875
PRODUCT SPECIFICATION
REV. 1.2.15 1/14/02
25
Applications Information
For additional applications information see Applications
Notes available from the factory.
To minimize component count, use of the following on-chip
circuits is recommended:
1.
ADC sampling clock.
2.
Clamp.
3.
Voltage reference
Optimum PLL Conguration Register (address 0x0C)
settings for typical modes are listed in Table 7. Unless
otherwise indicated, all modes are compliant with VESA or
SMPTE specications. For unlisted modes, values should be
adjusted to optimize performance.
By adjusting the values in the gain (GRP, GGY, GBP) and
offset (OSRO, OSGY, OSBP) registers, the input conversion
range can be matched to the incoming analog signals.
AC Coupled Digitizer
Shown in Figure 24 is an implementation of a video digitizer
with AC coupled YPBPRinputs. Horizontal sync input.
Output data is three channel 24-bit pixels with a maximum
rate of 140Ms/s. Data is clocked out on the negative edge of
DCK. HSOUT is delayed HSIN.
Control is through the serial port with 150
resistors
inserted to allow interfacing with 5V logic. If the serial bus is
operates with 3.3V levels, these resistors are unnecessary.
Figure 24. Schematic, VGA Digitizer, AC Coupled RGB
VPLL
VADC
VPLL
VDIG
REFOUT
F
R2
75
R6
3.3k
C2
C5
0.0039uF
0.039uF
C6
0.1uF
RN1
100
RN2
100
RN3
100
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
C3
F
.047uF
R3
75
C1
R1
75
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
C4
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
U1
FMS9875
43
44
46
47
73
9
4
21
15
41
40
38
45
48
3
36
10
22
23
24
25
16
30
20
8
12
14
18
28
29
32
42
49
59
61
71
84
90
92
93
94
6
98
97
96
87
88
26
27
33
37
39
5
7
11
13
17
19
50
60
62
72
85
91
1
2
89
74
75
100
95
99
31
34
35
83
82
81
80
79
78
77
76
58
57
56
55
54
53
52
51
70
69
68
67
66
65
64
63
86
NC1
NC2
NC4
NC5
NC7
BPIN
YGREF
CLAMP
RPIN
GND
NC3
NC6
YGIN
GND
BPREF
SDA
SCL
A0
A1
RPREF
HSIN
CKINV
GND
REFIN
REFOUT
PWRDN
DCK
HSOUT
VDDP
VDDA
VDDO
GND
ACSIN
DCSOUT
NC8
NC9
VDDA
COAST
XCK
LPF
DYG0
DYG1
DYG2
DYG3
DYG4
DYG5
DYG6
DYG7
DPR0
DPR1
DPR2
DPR3
DPR4
DPR5
DPR6
DPR7
DPB0
DPB1
DPB2
DPB3
DPB4
DPB5
DPB6
DPB7
DCK
R7
47
R8
47
R4
150
R5
150
A1
INVSCK
HSIN
Y
A0
PR
YDATA [7..0]
PBATA [7..0]
PRATA [7..0]
CLAMP
SDA
PB
DCK
SCL
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