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參數(shù)資料
| 型號(hào)： | FMS9875KGC100X |
| 英文描述： | 1-Bit Bidirectional Voltage-Level Translator With Auto Direction Sensing and +/-15-kV ESD Protect 6-SOT -40 to 85 |
| 文件頁(yè)數(shù)： | 5/29頁(yè) |
| 文件大?。?/td> | 481K |
| 代理商： | FMS9875KGC100X |
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FMS9875
PRODUCT SPECIFICATION
REV. 1.2.15 1/14/02
5
Pin Descriptions
Addressable Memory
Register Map
Pin
Name
Power and Ground
V
DDA
V
DDP
Pin No.
Pin Function Description
5, 7, 11, 13, 17, 19, 95, 99, 100
26, 27, 33, 37, 39
ADC Supply Voltages.
Provide a quiet noise free voltage.
PLL Supply Voltage.
Most sensitive supply voltage.
Provide a very quiet noise free voltage.
Digital Output Supply Voltage.
Decouple judiciously to
avoid propagation of switching noise.
Ground.
Returns for all power supplies. Connect ground
pins to a solid ground-plane.
Voltage Reference Input.
Common reference input to
RGB converters. Connect to VREFOUT, if internal
reference is used.
Voltage Reference Output.
Internal band-gap reference
output. Tie to ground through a 0.1μF capacitor.
V
DDO
50, 60, 62, 72, 85, 91
GND
1, 6, 8, 12, 14, 18, 28, 29, 32, 36, 38, 40,
41, 42, 49, 59, 61, 71, 84, 90, 92, 93, 94
98
V
REFIN
V
REFOUT
97
Name
PLLN
11-4
Address
00
Function
PLL divide ratio, MSBs.
PLLN + 1 = total number of
pixels per horizontal line.
PLL Control Register.
1. Lower four bits of PLL divide ratio.
2. PLL Subdivide phase.
3. PLL Subdivide ratio.
Gain, green/luminance channel.
Adjustable from 70 to
140%.
Gain, blue/P
B
channel.
Adjustable from 70 to 140%.
Gain, red/P
R
channel.
Adjustable from 70 to 140%.
Offset, green/luminance channel.
OSR
5-0
is stored in
the six upper register bits 7-2. Default value is decimal 32.
Default (hex)
69 (1693)
PLLCTRL
01
D0 (1693)
GGY
7-0
02
80
GBP
7-0
GRP
7-0
OSGY
5-0
03
04
05
80
80
80
OSBP
5-0
06
Offset, blue/P
B
channel.
OSR
5-0
is stored in the six
upper register bits 7-2. Default value is decimal 32.
80
OSRP
5-0
07
Offset, red/P
R
channel.
OSR
5-0
is stored in the six upper
register bits 7-2. Default value is decimal 32.
80
CD
7-0
08
Clamp delay.
Delay in pixels from trailing edge of
horizontal sync.
Clamp width.
Width of clamp pulse in pixels.
Configuration Register No. 1
80
CW
7-0
CONFIG 1
09
0A
80
F4
OSGY
5–0
X X
OSBP
5–0
X X
OSRP
5–0
X X
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