參數(shù)資料
型號(hào)： FMS9875KGC100X
英文描述： 1-Bit Bidirectional Voltage-Level Translator With Auto Direction Sensing and +/-15-kV ESD Protect 6-SOT -40 to 85
文件頁數(shù)： 26/29頁
文件大?。?/td> 481K
代理商： FMS9875KGC100X
PRODUCT SPECIFICATION
FMS9875
26
REV. 1.2.15 1/14/02
Printed Wiring Board Design Guidelines
Recommended strategy is to mount the FMS9875 over a
ground plane with carefully routed analog inputs and digital
outputs. All connections should be treated as transmission
lines to ensure that reflections due to mismatches are mini-
mized and ground return currents do not interfere with critical
signals.
Analog Inputs
Recommendations:
1.
Keep analog trace lengths short to minimize crosstalk.
Terminate analog inputs with 75
resistors, placed
close to the FMS9875 analog inputs, R
IN
, G
IN
and B
IN
.
By matching transmission line impedances, reflections
will be minimized.
Layout traces as 75
transmission lines.
2.
3.
4.
Avoid running analog traces near digital traces. Due to
the wide input bandwidth (400MHz) digital noise can
easily leak into analog inputs or cause excessive PLL
jitter.
5.
If necessary, limit bandwidth by adding a ferrite bead in
series with each RGB input as shown in Figure 25. A
Fair-Rite #2508051217Z0 is recommended. Alternatively,
bandwidth reduction using a shunt 10pF capacitor may
reduce snow (intensity noise) caused by HF noise riding
on the RGB input. Mismatches, reflections and noise
may cause ringing or distortion of the incoming video
signals.
6.
Locate the PLL filter close to the FMS9875 package and
clear of other signals.
7.
Bypass the reference with a 0.1μF capacitor to ground.
Figure 25. RGB Input Filter Options
Digital I/O
Recommendations:
1.
Route digital I/O signals clear of analog inputs.
2.
Terminate clock lines to reduce reflections. Treat clock
lines as transmission lines.
3.
Scale the HSIN input to 3.3V, using a resistor network
or a series 1 k
resistor.
4.
Limit Serial Port inputs voltages applied to SDA and
SDL pins with 150
resistors connected directly to the
pins.
5.
If necessary, to reduce reflections, EMI or spikes add a
50–200
resistor at each data output pin.
6.
If necessary, to reduce reflections, EMI or spikes add a
50–200
resistor at each data output pi.
7.
To minimize noise within the FMS9875, restrict the
capacitive load at the digital outputs to < 10pF.
Power and Ground
A schematic of the recommended power distribution is
shown in Figure 26. Note that:
1.
Analog and digital circuits are layed out over a common
solid ground plane.
2.
Each FMS9875 pin is decoupled with a 0.1μF capacitor.
3.
A group of pins may be de-coupled through a common
capacitor if no pin is more than 5 mm from the capacitor.
4.
A separate regulated supply is used for the phase-locked
loop power supply, V
DDP
.
Capacitors are attached to each PLL pin or pin-pair.
5.
R
IN
, G
IN
, B
IN
R, G, B INPUT
R1
75
L1
BEAD
C1
47 nF
C2
10pF
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FMS9884AKAC100 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 MQFP RoHS:否 制造商:Texas Instruments 輸入信號(hào)類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel
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