參數(shù)資料
型號: FM3808DK
廠商: Electronic Theatre Controls, Inc.
元件分類: DRAM
英文描述: 4Kb FRAM Serial 3V Memory
中文描述: 4Kb的鐵電串行3V的記憶
文件頁數(shù): 6/28頁
文件大小: 191K
代理商: FM3808DK
FM3808
Rev 1.1
May 2003
Page 6 of 28
Address
7FF4h
Description
Alarm – Hours
D7
D6
D5
D4
D3
D2
D1
D0
M
0
10 hours.1
10 hours.0
Hours.3
Hours2
Hours.1
Hours.0
/M
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.
Match: Setting this bit to 0 causes the Hours value to be used in the alarm match. Setting this bit to 1
causes the match circuit to ignore the Hours value.
Alarm – Minutes
D7
D6
D5
D4
7FF3h
D3
D2
D1
D0
M
10 min.2
10 min.1
10 min.0
Min.3
Min.2
Min.1
Min.0
/M
Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value
Match: Setting this bit to 0 causes the Minutes value to be used in the alarm match. Setting this bit to 1
causes the match circuit to ignore the Minutes value.
Alarm – Seconds
D7
D6
D5
D4
7FF2h
D3
D2
D1
D0
M
10 sec.2
10 sec.1
10 sec.0
Seconds.3
Seconds.2
Seconds.1
Seconds.0
/M
Contains the alarm value for the seconds and the mask bit to select or deselect the minutes value.
Match: Setting this bit to 0 causes the Seconds value to be used in the alarm match. Setting this bit to1
causes the match circuit to ignore the Seconds value.
User-Nonvolatile
D7
D6
D5
D4
7FF1h
D3
D2
D1
D0
7FF0h
This register is an uncommitted nonvolatile register.
Flags/Control
D7
D6
D5
D4
D3
D2
D1
D0
WDF
Watchdog Timer Flag. This read-only bit is set to 1 when the watchdog timer is allowed to reach 0
without being reset by the user. It is cleared to 0 when the Flags/Control register is read.
Alarm Flag. This read-only bit is set to 1 when the time and date match the values stored in the alarm
registers with the match bit(s) = 0. It is cleared when the Flags/Control register is read.
Power-fail Flag. This read-only bit is set to 1 when power falls below the power-fail interrupt threshold
V
TP
. It is cleared to 0 when the Flags/Control register is read.
Century Overflow Flag. This read-only bit is set to a 1 when the values in the years register overflows
from 99 to 00. This indicates a new century, such as going from 1999 to 2000 or 2099 to 2100. The user
should record the new century information as needed. This bit is cleared to 0 when the Flags/Control
register is read.
Invokes factory test mode. Users should always set this bit to 0.
Calibration Mode. When set to 1, the clock enters calibration mode. When CAL is set to 0, the clock
operates normally.
Write Time. Setting the W bit to 1 freezes updates of the timekeeping registers. The user can then write
them with updated values. Setting the W bit to 0 causes the contents of the time registers to be
transferred to the timekeeping counters. This bit affects registers 7FF9h - 7FFFh.
Read Time. Setting the R bit to 1 copies a static image of the timekeeping registers and places them in a
holding register. The user can then read them without concerns over changing values causing system
errors. The R bit going from 0 to 1 causes the timekeeping capture, so the bit must be returned to 0 prior
to reading again. This bit affects registers 7FF9h - 7FFFh.
AF
PF
CF
TST
CAL
W
R
WDF
AF
PF
CF
TST
CAL
W
R
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