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參數(shù)資料
| 型號： | FM3808DK |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | 4Kb FRAM Serial 3V Memory |
| 中文描述： | 4Kb的鐵電串行3V的記憶 |
| 文件頁數(shù)： | 12/28頁 |
| 文件大小： | 191K |
| 代理商： | FM3808DK |
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FM3808
Rev 1.1
May 2003
Page 12 of 28
Power Monitor
The FM3808 provides a power management scheme
with either power-fail interrupt or processor-reset
capability. It also controls the internal switch to
backup power for the timekeeper and protects the
memory from low-V
DD
access. The power monitor is
based on an internal band-gap reference circuit that
compares the V
DD
voltage to various thresholds.
The power monitor compares V
DD
to three thresholds.
The first is an interrupt threshold (V
TP
). When V
DD
drops below the V
TP
level, the event will set the
power fail flag PF (7FF0h bit D5). It also can drive
the INT pin as described in the Interrupts section.
The second threshold is the low V
DD
memory lockout
voltage V
LO
. This level prevents low voltage writes to
the FRAM array, which may otherwise result in
corrupted data. At this point, access to the memory
array and clock registers will be blocked until V
DD
rises above V
LO
. The lockout voltage V
LO
always trips
below V
TP
. When V
DD
drops below V
LO
, all inputs
will be ignored. On power up, the chip enable input
will be ignored while V
DD
is below V
LO
, but must be
pulled high prior to V
DD
reaching V
LO
.
At the third threshold, the internal supply switches
from V
DD
to V
BAK
for the timekeeper. This
switchover will occur at the level when V
DD
is less
than V
BAK
. When switchover occurs, the clock will
begin to draw power from V
BAK
rather than V
DD
. This
event may be above or below the V
TP
or V
LO
level
depending on whether a battery or capacitor backup is
used.
To conserve the life of the backup source, the power
monitor circuit is only operated from V
DD
. When V
DD
has dropped too low for the monitor to work, it ceases
operation. However, the power monitor will
reenergize as V
DD
rises on power up. On power-up,
after the band-gap energizes, the reverse sequence
will occur. As soon as the band gap is functional, it
will re-assert both selections for switch over and
power fail. As the V
DD
rises further, the device will
revert to the primary power source V
DD
, allowing
memory access and clock operation. As the V
DD
rises
above V
TP
, the power-fail condition will be removed.
Note that the PF flag will not be cleared until the
Flags/Control register is read.
The following figure illustrates the various events
tracked by the power monitor.
V
DD
V
TP
V
LO
V
TP
V
LO
V
BAK
V
BAK
V
RST
V
RST
Figure 4. Power Monitor Events
In the diagram, V
RST
is the voltage at which an active-
low interrupt will have sufficient drive strength to
pull the INT pin low.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FMA10A | General Purpose(Dual Digital Transistor)(通用(雙數(shù)字晶體管)) |
| FMA11A | Emitter Common (Dual Digital Transistors)(公共發(fā)射級(雙數(shù)字晶體管)) |
| FMA1 | General purpose (dual digital transistors) |
| FMA1A | General purpose (dual digital transistors) |
| FMA2A | Emitter common (dual digital transistors) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FM3808-S | 制造商:Ramtron International Corporation 功能描述:FRAM RTC 256K SMD 3808 TSOP32 |
| FM3808-SG | 制造商:Ramtron International Corporation 功能描述:FRAM RTC 256K SMD 3808 TSOP32 |
| FM380-A | 制造商:FORMOSA 制造商全稱:Formosa MS 功能描述:Silicon epitaxial planer type |
| FM380-AL | 制造商:FORMOSA 制造商全稱:Formosa MS 功能描述:Chip Schottky Barrier Diodes - Silicon epitaxial planer type |
| FM380-ALN | 制造商:FORMOSA 制造商全稱:Formosa MS 功能描述:Chip Schottky Barrier Diodes - Silicon epitaxial planer type |
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