- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382961 > FM3808DK (Electronic Theatre Controls, Inc.) 4Kb FRAM Serial 3V Memory PDF資料下載
參數(shù)資料
| 型號： | FM3808DK |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | 4Kb FRAM Serial 3V Memory |
| 中文描述： | 4Kb的鐵電串行3V的記憶 |
| 文件頁數(shù)： | 11/28頁 |
| 文件大?。?/td> | 191K |
| 代理商： | FM3808DK |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
FM3808
Rev 1.1
May 2003
Page 11 of 28
Watchdog Timer
The Watchdog timer is a free running down counter
that uses the 32 Hz clock (31.25 ms) derived from the
crystal oscillator. The oscillator must be running
(/OSCEN=0) for the watchdog to function. It begins
counting down from the value loaded in the
Watchdog Timer register (7FF7h).
The counter consists of a loadable register and a free
running counter. On power up, the watchdog timeout
value in 7FF7h is loaded into the counter load
register. Counting begins on power up and restarts
from the loadable value any time the Watchdog
Strobe WDS bit (7FF7h bit D7) is set to 1. The
counter is compared to terminal value of 0. If the
counter reaches this value, it causes an internal flag
and an optional interrupt output (see interrupts
below). The user can prevent the timeout interrupt by
setting WDS bit to 1 prior to the counter reaching 0.
This causes the counter to be reloaded with the
watchdog timeout value and to be restarted. As long
as the user sets the WDS bit prior to the counter
reaching the terminal value, the interrupt and flag
never occurs.
New timeout values can be written by setting the
watchdog write bit (7FF7h bit D6) to 0. When the
/WDW bit is 0 (from a previous operation), new
writes to the watchdog timeout value 7FF7h bits D5-
D0 allow the timeout value to be modified. When
/WDW is a 1, then writes to bits 7FF7h bits D4-D0
will be ignored. The /WDW function allows a user to
set the WDS bit without concern that the watchdog
timer value will be modified. A logical diagram of the
watchdog timer is shown below. Note that setting the
watchdog timeout value to 0 would be otherwise
meaningless and therefore disables the watchdog
function.
The output of the watchdog timer is a flag bit WDF
(7FF0h bit D7) that is set if the watchdog is allowed
to timeout. The flag is set upon a watchdog timeout
and cleared when the Flags/Control register is read by
the user. The user can also enable an optional
interrupt source to drive the INT pin if the watchdog
timeout occurs. The interrupt function is described on
page 13.
Oscillator
Clock
Divider
Counter
Watchdog
register
32.768 kHz
1 Hz
32 Hz
WDS
WDW
7FF7.5-0
Zero
Compare
WDF
7FF0.7
Load Register
Q
Q
D
write to
Watchdog
register
Figure 3. Watchdog Timer Block Diagram
相關PDF資料 |
PDF描述 |
|---|---|
| FMA10A | General Purpose(Dual Digital Transistor)(通用(雙數(shù)字晶體管)) |
| FMA11A | Emitter Common (Dual Digital Transistors)(公共發(fā)射級(雙數(shù)字晶體管)) |
| FMA1 | General purpose (dual digital transistors) |
| FMA1A | General purpose (dual digital transistors) |
| FMA2A | Emitter common (dual digital transistors) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| FM3808-S | 制造商:Ramtron International Corporation 功能描述:FRAM RTC 256K SMD 3808 TSOP32 |
| FM3808-SG | 制造商:Ramtron International Corporation 功能描述:FRAM RTC 256K SMD 3808 TSOP32 |
| FM380-A | 制造商:FORMOSA 制造商全稱:Formosa MS 功能描述:Silicon epitaxial planer type |
| FM380-AL | 制造商:FORMOSA 制造商全稱:Formosa MS 功能描述:Chip Schottky Barrier Diodes - Silicon epitaxial planer type |
| FM380-ALN | 制造商:FORMOSA 制造商全稱:Formosa MS 功能描述:Chip Schottky Barrier Diodes - Silicon epitaxial planer type |
發(fā)布緊急采購，3分鐘左右您將得到回復。