參數(shù)資料
型號(hào): FLEX10KA
廠商: Altera Corporation
英文描述: Embedded Programmable Logic Family
中文描述: 嵌入式可編程邏輯系列
文件頁數(shù): 5/114頁
文件大?。?/td> 1422K
代理商: FLEX10KA
Altera Corporation
5
FLEX 10K Embedded Programmable Logic Family Data Sheet
Notes:
(1)
(2)
(3)
The speed grade of this application is limited because of clock high and low specifications.
This application uses combinatorial inputs and outputs.
This application uses registered inputs and outputs.
The FLEX 10K architecture is similar to that of embedded gate arrays, the
fastest-growing segment of the gate array market. As with standard gate
arrays, embedded gate arrays implement general logic in a conventional
òsea-of-gatesó architecture. In addition, embedded gate arrays have
dedicated die areas for implementing large, specialized functions. By
embedding functions in silicon, embedded gate arrays provide reduced
die area and increased speed compared to standard gate arrays. However,
embedded megafunctions typically cannot be customized, limiting the
designers options. In contrast, FLEX 10K devices are programmable,
providing the designer with full control over embedded megafunctions
and general logic while facilitating iterative design changes during
debugging.
Each FLEX 10K device contains an embedded array and a logic array. The
embedded array is used to implement a variety of memory functions or
complex logic functions, such as digital signal processing (DSP),
microcontroller, wide-data-path manipulation, and data-transformation
functions. The logic array performs the same function as the sea-of-gates
in the gate array: it is used to implement general logic, such as counters,
adders, state machines, and multiplexers. The combination of embedded
and logic arrays provides the high performance and high density of
embedded gate arrays, enabling designers to implement an entire system
on a single device.
Table 5. FLEX 10K Performance
Application
Resources
Used
Performance
Units
LEs
EABs -1 Speed Grade -2 Speed Grade -3 Speed Grade -4 Speed Grade
16-bit loadable
counter,
16-bit accumulator,
Note (1)
16-to-1 multiplexer,
Note (2)
256
×
8 RAM read
cycle speed,
256
×
8 RAM write
cycle speed,
Note (1)
16
0
204
166
125
MHz
16
0
204
166
125
95
MHz
10
0
4.5
5.8
6.0
7.0
ns
Note (3)
0
1
185
118
103
84
MHz
Note (3)
0
1
106
86
77
63
MHz
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參數(shù)描述
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