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參數(shù)資料
| 型號： | FEDS81V26000-01 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 1,114,112-Word X 24-Bit Field Memory |
| 中文描述： | 1114112字× 24位場記憶 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大小： | 160K |
| 代理商： | FEDS81V26000-01 |
FEDS81V26000-02
OKI Semiconductor
MS81V26000
5/20
PIN DESCRIPTION
Serial Write Clock: SWCK
The SWCK latches the input data on chip when WE is high, and also increments the internal write address pointer.
Data-in setup time tDS, and hold time tDH are referenced to the rising edge of SWCK.
Write Reset: RSTW
RSTW is used to set the internal write address pointer. RSTW setup and hold times are referenced to the rising
edge of SWCK. The SWCK latches the write address data (21bits serial LSB) from WAD.
Write Enable: WE
WE is used for data write enable/disable control. WE high level enables the input, and WE low level disables the
input and holds the internal write address pointer. There are no WE disable time (low) and WE enable time (high)
restrictions, because the MS81V26000 is in fully static operation as long as the power is on. Note that WE setup
and hold times are referenced to the rising edge of SWCK. The latency for the write operation control by WE is 4.
After write reset, WE must remain low for more than 1600 ns (tFWD). After write reset, the write operation at
address 0 is started after a time tWL form the cycle in which WE is brought high.
After write reset, WE should be remained high for 2 cycles after driving WE high first.
Input Enable: IE
IE is used to enable/disable writing into memory. IE high level enables writing. The internal write address pointer
is always incremented by cycling SWCK regardless of the IE level. Note that IE setup and hold times are
referenced to the rising edge of SWCK. The latency for the write operation control by IE is 4.
Write Address Input: WAD
These pins are used for write address input.
Data Inputs: (DI0-23)
These pins are used for serial data inputs.
Write Reset: RSTW
RSTW is used to set the internal write address pointer. RSTW setup and hold times are referenced to the rising
edge of SWCK. The SWCK latches the write address data (21bits serial LSB) from WAD.
Data Out: (DO0-23)
These pins are used for serial data outputs.
Serial Read Clock: SRCK
Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when RE is high during a read
operation. The SRCK input increments the internal read address pointer when RE is high.
The three-state output buffer provides direct TTL compatibility (no pullup resistor required). Data out is the same
polarity as data in. The output becomes valid after the access time interval tAC that begins with the rising edge of
SRCK. *There are no output valid time restriction on MS81V26000.
Read Reset: RSTR
RSTR is used to set the internal read address pointer. RSTR setup and hold times are referenced to the rising edge
of SRCK. The SWCK latches the read address data (21bits serial LSB) from RAD.
Read Enable: RE
The function of RE is to gate of the SRCK clock for incrementing the read pointer. When RE is high before the
rising edge of SRCK, the read pointer is incremented. When RE is low, the read pointer is not incremented. RE
setup times (tRENS and tRDSS) and RE hold times (tRENH and tRDSH) are referenced to the rising edge of the
SRCK clock.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
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| FEDS82V48540-01 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:393,216-Word × 32-Bit × 4-Bank FIFO-SGRAM |
| FEDSM2000-11043 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DUAL EMISSION LASER INDUCED FLUORESCENCE TECHNIQUE (DELIF) FOR OIL FILM THICKNESS AND TEMPERATURE MEASUREMENT |
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