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參數資料
| 型號： | FEDS81V26000-01 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 1,114,112-Word X 24-Bit Field Memory |
| 中文描述： | 1114112字× 24位場記憶 |
| 文件頁數： | 10/20頁 |
| 文件大?。?/td> | 160K |
| 代理商： | FEDS81V26000-01 |
FEDS81V26000-02
OKI Semiconductor
OPERATION MODE
Write Operation Cycle
The write operation is controlled by four control signals, SWCK, RSTW, WE and IE. The write operation is
accomplished by cycling SWCK, and holding WE high after the write address pointer reset operation or RSTW.
RSTW must be performed for internal circuit initialization before write operation. WE must be low before and
after the reset cycle (t
LWE
+ t
WAE
+ t
FWD
).
Each write operation, which begins after RSTW must contain at least 231 active write cycles, i.e., SWCK cycles
while WE and IE are high.
Settings of WE and IE to the operation mode of Write address pointer and Data input.
WE
IE
Internal Write address pointer
H
H
H
L
L
X
Halted
X indicates "don't care"
Read Operation Cycle
The read operation is controlled by four control signals, SRCK, RSTR, RE, and OE. The read operation is
accomplished by cycling SRCK, and holding both RE and OE high after the read address pointer reset operation or
RSTR.
Each read operation, which begins after RSTR, must contain at least 231 active read cycles, i.e., SRCK cycles
while RE and OE are high. RE must be low before and after the reset cycle (t
LRE
+ t
RAE
+ t
FWD
).
Settings of RE and OE to the operation mode of read address pointer and Data output.
RE
OE
Internal Read address pointer
H
H
H
L
L
H
L
L
Power-up and Initialization
To assure proper operation of this Memory, place an interval of at least 200
μ
s after Vcc has stabilized to a value
within the range of recommended operating conditions after power-up prior to the operation start. After this 200
μ
s
stabilization interval, the following initialization sequence must be performed. Because the read and write address
pointers are undefined after power-up, a minimum of 150 dummy write operations (SWCK cycles) and read
operations (SRCK cycles) must be performed, followed by an RSTW operation and an RSTR operation, to
properly initialize the write and the read address pointer.
MS81V26000
10/20
Data input (Latency 4)
Input
Incremented
Not input
Data output (Latency 4)
Output
High impedance
Output
High impedance
Incremented
Halted
相關PDF資料 |
PDF描述 |
|---|---|
| FEDS82V16520A-01 | 262,144-Word 】 32-Bit 】 2-Bank SGRAM |
| FEDS82V48540-01 | 393,216-Word 】 32-Bit 】 4-Bank FIFO-SGRAM |
| FEP16AT | Fast Rectifiers (Glass Passivated) |
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| FEP16DTA | Fast Rectifiers (Glass Passivated) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| FEDS82V16520A-01 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:262,144-Word × 32-Bit × 2-Bank SGRAM |
| FEDS82V48540-01 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:393,216-Word × 32-Bit × 4-Bank FIFO-SGRAM |
| FEDSM2000-11043 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DUAL EMISSION LASER INDUCED FLUORESCENCE TECHNIQUE (DELIF) FOR OIL FILM THICKNESS AND TEMPERATURE MEASUREMENT |
| FEDWC375/12014+ | 制造商: 功能描述: 制造商:undefined 功能描述: |
| FEE160-2-2NL | 制造商:Pulse Electronics Corporation 功能描述: |
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