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Nap mode
The nap mode reduces power consumption when the Finger-
Chip
T is not used. The nap mode is enabled when RESET is
high. At this moment, all flip–flop inside the circuit are posi-
tioned, analog cells do not dissipate power and only bandgap
and circuitry connected to the input clock PCLK consume
power. User may also stop the clock: this is the minimal power
consumption mode.
To summarize, nap mode is when:
– RESET is high
– optionally PCLK is set to low or high
To restart from nap mode, it is recommended this sequence is
followed:
– start the clock PCLK
– set RESET to low.
The TS83148 is a 8 bit/50MSPS low power consumption ADC,
with a nap mode, overflow and underflow signals. See the
TS83148 datasheet for more information.
Image rate and speed of the sweeping
An 8 MHz clock enables the output of 714 images per second:
one image = (30+10)x280=11200 clock pulses
If we assume that we need at least 15 pixels recovery between
two images to reconstruct the complete image, that gives the
maximum speed of the sweeping:
15 x 0.05 x 714 = 535 mm/s or 21 inch/s
that is a very high speed to sweep a finger, and user will prob-
ably not need such a rate.
We recommend to have less than 10 pixels of displacement
between two images (so 20 pixels of recovery between two
images), as 500
mm is roughly the spatial frequency of the
ridges of the fingerprints. A speed of 200 mm/s is already fast,
so that we recommend a clock rate of 4.5 MHz, but this has to
be confirmed:
clock rate = 11200 x sweep speed / (displacement for 1 image).
Conclusion
This is why we propose a two–step approach for development:
first use our evaluation board to adjust the different parameters
to get the best results. Once this is defined, make your final
board that will be drastically simplified compared to the evalua-
tion board.
SWITCHING PERFORMANCES
Parameter
Test level
Symbol
Min
Typ
Max
Unit
Clock frequency
FPCLK
0.125
4.0
8.0
MHz
Minimum clock pulse width (high)
TChigh
4000
125
62.5
ns
Minimum clock pulse width (low)
TClow
4000
125
62.5
ns
Setup time of RESET to PCLK
TR setup
0
ns
Output delay from PCLK to SCLK
TPS
44
ns
Output delay from PCLK to LCLK
TPL
40
ns
Output delay from PCLK to FCLK
TPF
45
ns
Aperture of AVIDEO signal for sampling
TAVIDEO
"20
ns
Note
Outputs connected to Cload = 120 pF.