參數(shù)資料
型號(hào): FBL2031BB
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: 9-bit BTL 3.3V latched/registered/pass-thru Futurebus transceiver
中文描述: FBL SERIES, 9-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PQFP52
封裝: SOT-379, 52 PIN
文件頁數(shù): 12/16頁
文件大?。?/td> 165K
代理商: FBL2031BB
Philips Semiconductors
Product specification
FBL2031
9-bit BTL 3.3V latched/registered/pass-thru
Futurebus+ transceiver
2000 Apr 18
12
AC SETUP REQUIREMENTS
(Commercial)
LIMITS
SYMBOL
PARAMETER
TEST
T
amb
= +25
°
C, V
CC
= 3.3V,
T
amb
= –40 to +85
°
C,
CC
= 3.3V
±
10%,
UNIT
CONDITION
C
L
= 50pF (A side) / C
D
= 30pF (B side)
R
L
= 500
(A side) / R
U
= 16.5
(B side)
TYP
MIN
1.3
1.3
1.0
1.0
5.0
4.0
0.0
0.0
3.0
3.0
MIN
1.5
1.5
1.0
1.0
6.0
4.5
0.0
0.0
3.0
3.0
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
Setup time
An to LCAB
Hold time
An to LCAB
Setup time
Bn to LCBA
Hold time
Bn to LCBA
Pulse width, High or Low
LCAB or LCBA
Waveform 4
ns
Waveform 4
ns
Waveform 4
ns
Waveform 4
ns
Waveform 4
ns
AC WAVEFORMS
íí
íí
t
h
V
M
t
s
t
PZL
Input
Output
V
M
V
M
V
M
t
PHL
V
M
t
PLH
V
M
V
M
V
M
V
M
t
PHL
t
PLH
Output
An, Bn
An, Bn
V
M
V
M
t
SK
(o)
An
OEA
V
M
V
M
t
PLZ
V
M
V
OL
+0.3V
An
OEA
V
M
V
M
V
M
V
OH
-0.3V
OV
t
PHZ
t
PZH
NOTE:
V
M
= 1.55V for Bn, V
M
= 1.5V for all others.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Input
íí
íí
íííí
íííí
t
h
An, Bn
LCAB, LCBA
V
M
V
M
1/f
MAX
t
s
t
w
(L)
t
w
(H)
Waveform 1. Propagation Delay for Data
or Output Enable to Output
Waveform 2. Propagation Delay for Data
or Output Enable to Output
Waveform 3. Output to Output Skew
Waveform 4. Setup and Hold Times,
Pulse Widths and Maximum Frequency
Waveform 5. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
Waveform 6. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
t
w
(input)
t
w
(output)
SG00062
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