參數(shù)資料
型號(hào)： FAN6920MRMY
廠商： Fairchild Semiconductor
文件頁(yè)數(shù)： 22/24頁(yè)
文件大?。?/td> 1490K
描述： IC PWM CTLR PFC/QUASI-RES 16SOP
標(biāo)準(zhǔn)包裝： 1
模式： 臨界傳導(dǎo)（CRM）
電流 - 啟動(dòng)： 20µA
電源電壓： 12 V ~ 25 V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOP
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： FAN6920MRMYDKR
 
?2010 Fairchild Semiconductor Corporation
 
www.fairchildsemi.com
FAN6920MR " Rev. 1.0.8
22
 
Output Over-Voltage Protection (DET Pin)
Referring to Figure 46, during the discharge time of
PWM   transformer   inductor;   the   voltage   across   on
auxiliary winding is reflected from secondary winding
and therefore the flat voltage on the DET pin is
proportional to the output voltage. FAN6920MR can
sample this flat voltage level after a t
OFF
 blanking time to
perform   output   over-voltage   protection.   This   t
OFF
 
blanking time is used to ignore the voltage ringing from
leakage inductance of PWM transformer. The sampling
flat voltage level is compared with internal threshold
voltage 2.5 V and, once the protection is activated,
FAN6920MR enters auto-recovery protection.
The controller can protect rapidly by this kind of cycle-
by-cycle sampling method in the case of output over
voltage. The protection voltage level can be determined
by the ratio of external resistor divider R
A
 and R
DET
. The
flat voltage on DET pin can be expressed by the
following equation:
(
)
A
DET
A
S
O
DET
A
R
N   N    V
R
R
=
?nbsp  ?/DIV>
+
 
(2)
A
D
E
T
A
A
O
R
R
R
N
N
+
?/DIV>
?/DIV>
V
D  E  T
P W   M
G  a t e
V
A  U  X
P
A
O
N
N
V
F
C
?/DIV>
_
0 . 3 V
t
O  F F
B  l a n k i n g
S  a m  p l i n g
H  e r e
A
O
N
N
?/DIV>
t
t
t
 
Figure 46. Operation Waveform of Output
Over-Voltage Detection
Open-Loop, Short-Circuit, and Overload Protection
(FB Pin)
FB
V
O
Open-Loop
Short C ircuit / O verload
 
Figure 47. FB Pin Open-Loop, Short Circuit,
and Overload Protection
Referring to Figure 47; outside of FAN6920MR, the FB
pin is connected to the collector of transistor of an opto-
coupler. Inside, the FB pin is connected to an internal
voltage bias through a resistor of around 5 kW.
As the output loading is increased, the output voltage is
decreased and the sink current of the transistor of the
opto-coupler on primary side is reduced. The FB pin
voltage is increased by internal voltage bias. In the case
of   an   open   loop,   output   short-circuit,   or   overload
condition; this sink current is further reduced and the FB
pin voltage is pulled HIGH by internal bias voltage.
When the FB pin voltage is higher than 4.2 V for 50 ms, 
the FB pin protection is activated.
Under-Voltage Lockout (UVLO, VDD Pin)
Referring to Figure 38 and Figure 39, the turn-on and
turn-off V
DD
  threshold voltages are fixed at 18 V and
10 V, respectively. During startup, the hold-up capacitor
(V
DD
  capacitor) is charged by HV startup current until
V
DD
  voltage reaches the turn-on voltage. Before the
output voltage rises to rated voltage and delivers energy
to the V
DD
 capacitor from auxiliary winding, this hold-up
capacitor must sustain the V
DD
  voltage energy for
operation. When V
DD
  voltage reaches turn-on voltage,
FAN6920MR   starts   all   switching   operation   if   no
protection is triggered before V
DD
 voltage drops to turn-
off voltage V
DD-PWM-OFF
.
 
 
 
 
 
 
 
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