參數(shù)資料
型號(hào)： FAN6920MRMY
廠商： Fairchild Semiconductor
文件頁(yè)數(shù)： 21/24頁(yè)
文件大小： 1490K
描述： IC PWM CTLR PFC/QUASI-RES 16SOP
標(biāo)準(zhǔn)包裝： 1
模式： 臨界傳導(dǎo)（CRM）
電流 - 啟動(dòng)： 20µA
電源電壓： 12 V ~ 25 V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOP
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： FAN6920MRMYDKR
 
?2010 Fairchild Semiconductor Corporation
 
www.fairchildsemi.com
FAN6920MR " Rev. 1.0.8
21
 
V
AUX
 becomes higher as well. FAN6920MR also clamps
the DET pin voltage and flows out current I
DET
. Since the
current   I
DET
   is   in   accordance   with   V
AUX
   voltage,
FAN6920MR depends on this current during t
ON
  to
regulate the current limit level of the PWM switch to
perform high / low line over-power compensation.
As the input voltage increases, the reflected voltage on
the auxiliary winding V
AUX
  becomes higher as well as
the current I
DET
 and the controller regulates the V
LIMIT
 to
a lower level.
The R
DET
 resistor is connected from auxiliary winding to
the DET pin. Engineers can adjust this R
DET
 resistor to
get proper V
LIMIT
 voltage to fit the specification of over-
power or over-current protection. The characteristic
curve of I
DET
 current vs. V
LIMIT
 voltage on CSPWM pin is
shown in Figure 44.
(
)
DET
IN
A
P
DET
V    N   N
R
=    ?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
 
(1)
where V
IN
  is input voltage; N
A
  is turn number of
auxiliary winding; and N
P
  is turn number of primary
winding.
 
Figure 43. Relationship between V
AUX
 and V
IN
 
0
1 0 0
2 0 0
3 0 0
4 0 0
5 0 0
6 0 0
3 0 0
4 0 0
5 0 0
6 0 0
7 0 0
8 0 0
9 0 0
I
DE T
(?A )
 
Figure 44. I
DET
 Current vs. V
LIMIT
 Voltage
Characteristic Curve
Leading-Edge Blanking (LEB)
When the PFC or PWM switches are turned on, a
voltage spike is induced on the current-sense resistor
due to the reciprocal effect by reverse-recovery energy
of the output diode and C
OSS
  of power MOSFET. To
prevent this spike, a leading-edge blanking time is built-
in   and   a   small   RC   filter   (e.g.   100 ?   470 pF)   is
recommended between the CSPWM pin and GND.
Protection for PWM Stage
VDD Pin Over-Voltage Protection (OVP)
V
DD
  over-voltage protection prevents device damage
once V
DD
  voltage is higher than device stress rating
voltage. In the case of V
DD
 OVP, the controller stops all
switching   operation   immediately   and   enters   auto-
recovery protection.
Adjustable Over-Temperature Protection and
Externally Protection Triggering (RT Pin)
Figure 45 is a typical application circuit with an internal
block of RT pin. As shown, a constant current I
RT
 flows
out from the RT pin, so the voltage V
RT
 on the RT pin
can be obtained as I
RT
 current multiplied by the resistor,
which consists of NTC resistor and R
A
 resistor. If the RT
pin voltage is lower than 0.8 V and lasts for a debounce
time, auto-recovery protection is activated and stops all
PFC and PWM switching.
RT pin is usually used to achieve over-temperature
protection with a NTC resistor and provide external
protection triggering for additional protection. Engineers
can use an external triggering circuit (e.g. transistor) to
pull the RT pin low and activate controller auto-recovery
protection.
Generally, the external protection triggering needs to
activate rapidly since it is usually used to protect the
power system from abnormal conditions. Therefore, the
protection debounce time of the RT pin is set to around
110 祍 once the RT pin voltage is lower than 0.5 V.
For     over-temperature     protection,     because     the
temperature does not change immediately; the RT pin
voltage is reduced slowly as well. The debounce time
for adjustable OTP should not need a fast reaction. To
prevent improper protection triggering on the RT pin due
to exacting test condition (e.g. lightning test); when the
RT pin triggering voltage is higher than 0.5 V, the
protection debounce time is set to around 10 ms. To
avoid improper triggering on the RT pin, add a small
value capacitor (e.g. 1000 pF) paralleled with NTC and
the R
A
 resistor.
A u to -
R e c o v e r y
P r o te c tio n
0 .8 V
R T
I RT = 1 0 0 ?A
FA N 6 9 2 0 M R
Ad ju s ta b le O v e r -T e m p e r a tu r e P r o te c tio n  
a n d Ex te r n a l P r o te c tio n  T r ig g e r in g  
N T C
R
RT
12
0 .5 V
D e b o u n c e
T im e
1 0 0 ?s
1 0 m s
 
Figure 45. Adjustable Over-Temperature Protection
0V
0 V
t
O F F
t
O N
V
A U X
= - [ V
IN
* ( N a /N p ) ]
D  E T p i n v o l t a g e i s c l a m  p e d
d u r i n g t
ON
  p e r i o d .
V
DET
 
OPWM
V
A X
 
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