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| 型號(hào)： | EVAL-ADM2491EEBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADM2491 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，收發(fā)器，RS-485 |
| 已用 IC / 零件： | ADM2491 |
| 已供物品： | 板 |
ADM2491E
Rev. B | Page 14 of 16
APPLICATIONS INFORMATION
ISOLATED POWER SUPPLY CIRCUIT
The ADM2491E requires isolated power capable of 5 V at up to
approximately 75 mA (this current is dependent on the data
rate and termination resistors used) to be supplied between the
VDD2 and the GND2 pins. A transformer driver circuit with a
center-tapped transformer and LDO can be used to generate the
isolated 5 V supply, as shown in Figure 28. The center-tapped
transformer provides electrical isolation of the 5 V power
supply. The primary winding of the transformer is excited with
a pair of square waveforms that are 180° out of phase with each
other. A pair of Schottky diodes and a smoothing capacitor are
used to create a rectified signal from the secondary winding.
The ADP3330 linear voltage regulator provides a regulated
power supply to the bus-side circuitry (VDD2) of the
ADM2491E.
ISOLATION
BARRIER
VCC
78253
SD103C
22F
10F
5V
OUT
IN
SD
ERR
NR
GND
VCC
VDD1
VDD2
GND1
GND2
ADP3330
ADM2491E
06985-
028
TRANSFORMER
DRIVER
VCC
+
Figure 28. Isolated Power Supply Circuit
PCB LAYOUT
The ADM2491E isolated RS-485 transceiver requires no external
interface circuitry for the logic interfaces. Power supply bypass-
ing is required at the input and output supply pins (see Figure 29).
Bypass capacitors are conveniently connected between Pin 1
and Pin 2 for VDD1 and between Pin 15 and Pin 16 for VDD2. The
capacitor value should be between 0.01 F and 0.1 F. The total
lead length between both ends of the capacitor and the input
power supply pin should not exceed 20 mm. Bypassing between
Pin 1 and Pin 8 and between Pin 9 and Pin 16 should also be
considered unless the ground pair on each package side is
connected close to the package.
VDD1
GND1
RxD
RE
DE
TxD
NC
GND1
VDD2
GND2
A
B
NC
Z
Y
GND2
NC = NO CONNECT
ADM2491E
06985-
029
Figure 29. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, care
should be taken to ensure that board coupling across the isola-
tion barrier is minimized. Furthermore, the board layout should
be designed such that any coupling that does occur equally affects
all pins on a given component side. Failure to ensure this could
cause voltage differentials between pins exceeding the absolute
maximum ratings of the device, thereby leading to latch-up or
permanent damage.
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