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參數(shù)資料
| 型號： | EVAL-ADF4154EBZ1 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR ADF4154EB1 |
| 標準包裝： | 1 |
| 主要目的： | 計時，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4154 |
| 主要屬性： | 單路分數(shù)-N PLL |
| 次要屬性： | 19.2MHz PFD 圖形用戶界面 |
| 已供物品： | 板，線纜，軟件 |
| 相關產品： | ADF4154BCPZ-ND - IC FRACTION-N FREQ SYNTH 20LFCSP ADF4154BRU-REEL7-ND - IC FRACTION-N FREQ SYNTH 16TSSOP ADF4154BCPZ-RL7-ND - IC FRACTION-N FREQ SYNTH 20LFCSP ADF4154BRUZ-RL7TR-ND - IC FRACTION-N FREQ SYNTH 16TSSOP ADF4154BRUZ-RL-ND - IC FRACTION-N FREQ SYNTH 16TSSOP ADF4154BRU-REEL-ND - IC FRACTION-N FREQ SYNTH 16TSSOP ADF4154BCPZ-RL-ND - IC FRACTION-N FREQ SYNTH 20LFCSP ADF4154BRUZ-ND - IC FRAC-N FREQ SYNTH 16-TSSOP ADF4154BRU-ND - IC FRAC-N FREQ SYNTH 16-TSSOP |
ADF4154
Data Sheet
Rev. C | Page 10 of 24
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4154 allows the user to
access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 (see Table 8).
Figure 18 shows the MUXOUT section in block diagram form.
The N-channel, open-drain, analog lock detect should be
operated with an external pull-up resistor of 10 k nominal.
When lock has been detected, the lock detect is high with
narrow low-going pulses.
R-DIVIDER OUTPUT
N-DIVIDER OUTPUT
ANALOG LOCK DETECT
DGND
CONTROL
MUX
MUXOUT
DVDD
LOGIC LOW
FAST-LOCK CONTROL
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
04833-
018
LOGIC HIGH
Figure 18. MUXOUT Schematic
INPUT SHIFT REGISTERS
The ADF4154 digital section includes a 4-bit R value, a 9-bit
RF N value, a 12-bit RF FRAC value, and a 12-bit interpolator
modulus value/fast-lock timer. Data is clocked MSB first into
the 24-bit shift register on each rising edge of CLK.
Data is transferred from the shift register to one of four latches
on the rising edge of LE. The destination latch is determined by
the state of the two control bits (C2 and C1) in the shift register.
These are the two LSBs, DB1 and DB0, as shown in Figure 2.
The truth table for these bits is shown in Table 5. Table 6 shows
a summary of how the latches are programmed.
PROGRAM MODES
in the ADF4154.
The ADF4154 programmable modulus is double buffered,
meaning that two events must occur before the part can use a
new modulus value. The first event is that the new modulus value
must be latched into the device by writing to the R-divider register,
and the second event is that a new write must be performed on
the N-divider register. Therefore, whenever the modulus value
is updated, the N-divider register must be written to so that the
modulus value is loaded correctly.
Table 5. C2 and C1 Truth Table
Control Bits
C2
C1
Data Latch
0
N-divider register
0
1
R-divider register
1
0
Control register
1
Noise and spur register
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADF4156EBZ1 | 制造商:Analog Devices 功能描述:EVAL BOARD - Bulk |
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| EVAL-ADF4193EBZ1 | 功能描述:BOARD EVALUATION EB1 FOR ADF4193 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
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