參數(shù)資料
型號(hào)： EVAL-ADF4154EBZ1
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/24頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR ADF4154EB1
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，頻率合成器
嵌入式： 否
已用 IC / 零件： ADF4154
主要屬性： 單路分?jǐn)?shù)-N PLL
次要屬性： 19.2MHz PFD 圖形用戶界面
已供物品： 板，線纜，軟件
相關(guān)產(chǎn)品： ADF4154BCPZ-ND - IC FRACTION-N FREQ SYNTH 20LFCSP
ADF4154BRU-REEL7-ND - IC FRACTION-N FREQ SYNTH 16TSSOP
ADF4154BCPZ-RL7-ND - IC FRACTION-N FREQ SYNTH 20LFCSP
ADF4154BRUZ-RL7TR-ND - IC FRACTION-N FREQ SYNTH 16TSSOP
ADF4154BRUZ-RL-ND - IC FRACTION-N FREQ SYNTH 16TSSOP
ADF4154BRU-REEL-ND - IC FRACTION-N FREQ SYNTH 16TSSOP
ADF4154BCPZ-RL-ND - IC FRACTION-N FREQ SYNTH 20LFCSP
ADF4154BRUZ-ND - IC FRAC-N FREQ SYNTH 16-TSSOP
ADF4154BRU-ND - IC FRAC-N FREQ SYNTH 16-TSSOP
ADF4154
Data Sheet
Rev. C | Page 18 of 24
INITIALIZATION SEQUENCE
The following initialization sequence should be followed after
powering up the part:
1. Clear all test modes by writing all 0s to the noise and spur
register.
2. Select the noise and spur mode required for the application
by writing to the noise and spur register. For example, writing
Hex 0003C7 to the part selects low noise mode.
3. Enable the counter reset in the control register by writing a
1 to DB2 and selecting the required settings in the control
register.
4. Load the R-divider register (with the load control bit [DB23]
set to 0).
5. Load the N-divider register.
6. Disable the counter reset by writing a 0 to DB2 in the
control register.
The part should now lock to the set frequency.
RF SYNTHESIZER: A WORKED EXAMPLE
This equation governs how the synthesizer should be
programmed.
RFOUT = [INT + (FRAC/MOD)] × [fPFD]
(3)
where:
RFOUT is the RF frequency output.
INT is the integer division factor.
FRAC is the fractionality.
MOD is the modulus.
The PFD frequency can be calculated as follows:
fPFD = [REFIN × (1 = D)/R]
(4)
where:
REFIN is the reference frequency input.
D is the value of the RF REFIN doubler bit.
R is the RF reference division factor.
For example, in a GSM 1800 system, where a 1.8 GHz RF
frequency output (RFOUT) is required, a 13 MHz reference
frequency input (REFIN) is available and a 200 kHz channel
resolution (fRES) is required on the RF output.
RES
IN f
REF
MOD
/
=
65
kHz
200
MHz/
13
=
MOD
From Equation 4,
fPFD = [13 MHz × (1 + 0)/1] = 13 MHz
(5)
(
)
65
FRAC
INT
MHz
13
GHz
8
.
1
+
×
=
(6)
where:
INT is 138.
FRAC is 30.
MODULUS
The choice of modulus (MOD) depends on the reference signal
(REFIN) available and the channel resolution (fRES) required at
the RF output. For example, a GSM 1800 system using a 13 MHz
REFIN sets the modulus to 65, resulting in meeting the required
RF output resolution (fRES) of 200 kHz (13 MHz/65).
REFERENCE DOUBLER AND REFERENCE DIVIDER
The on-chip reference doubler allows the input reference signal
to be doubled. This is useful for increasing the PFD comparison
frequency, which in turn improves the noise performance of the
system. For example, doubling the PFD frequency usually
results in an improvement in noise performance of 3 dB. It is
important to note that the PFD cannot operate with frequencies
greater than 32 MHz due to a limitation in the speed of the Σ-Δ
circuit of the N-divider.
12-BIT PROGRAMMABLE MODULUS
Unlike most fractional-N PLLs, the ADF4154 allows the user
to program the modulus over a 12-bit range. Therefore, several
configurations of the ADF4154 are possible for an application by
varying the modulus value, the reference doubler, and the 4-bit
R-counter.
For example, consider an application that requires a 1.75 GHz
RF and a 200 kHz channel step resolution. The system has a
13 MHz reference signal.
One possible setup is feeding the 13 MHz REFIN directly into
the PFD and programming the modulus to divide by 65, which
results in the required 200 kHz resolution.
Another possible setup is using the reference doubler to create a
26 MHz input frequency from the 13 MHz REFIN signal. The
26 MHz signal is then fed into the PFD, which programs the
modulus to divide by 130. This setup also results in 200 kHz
resolution, plus it offers superior phase noise performance
compared with the previous setup.
The programmable modulus is also very useful for multi-
standard applications. If a dual-mode phone requires PDC and
GSM 1800 standards, the programmable modulus is a huge
benefit. The PDC requires a 25 kHz channel step resolution,
whereas the GSM 1800 requires a 200 kHz channel step
resolution. A 13 MHz reference signal could be fed directly to
the PFD. The modulus would be programmed to 520 when in
PDC mode (13 MHz/520 = 25 kHz). The modulus would be
reprogrammed to 65 for GSM 1800 operation (13 MHz/65 =
200 kHz). It is important that the PFD frequency remains con-
stant (13 MHz). By keeping the PFD constant, the user can
design a one-loop filter that can be used in both setups without
running into stability issues. The ratio of the RF frequency to
the PFD frequency affects the loop design. By keeping this
relationship constant, the same loop filter can be used in both
applications.
SPURIOUS OPTIMIZATION AND FAST LOCK
The ADF4154 can be optimized for low spurious signals by
using the noise and spur register. However, to achieve fast-lock
time, a wider loop bandwidth is needed. Note that a wider loop
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-ADF4156EBZ1 制造商:Analog Devices 功能描述:EVAL BOARD - Bulk
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