參數(shù)資料
型號(hào)： EVAL-ADE7756EB
廠商： Analog Devices, Inc.
英文描述： Active Energy Metering IC with Serial Interface
中文描述： 有源電能計(jì)量IC串行接口
文件頁(yè)數(shù)： 5/32頁(yè)
文件大?。?/td> 347K
代理商： EVAL-ADE7756EB
REV. 0
ADE7756
–5–
TIMING CHARACTERISTICS
1, 2
Parameter
A, B Versions
Unit
Test Conditions/Comments
Write Timing
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
Read Timing
t
9
20
150
150
10
5
6.4
4
100
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
μ
s (min)
μ
s (min)
ns (min)
CS
falling edge to first SCLK falling edge.
SCLK logic high pulsewidth.
SCLK logic low pulsewidth.
Valid Data Setup time before falling edge of SCLK.
Data Hold time after SCLK falling edge.
Minimum time between the end of data byte transfers.
Minimum time between byte transfers during a serial write.
CS
Hold time after SCLK falling edge.
4
μ
s (min)
Minimum time between read command (i.e., a write to Communication
Register) and data read.
Minimum time between data byte transfers during a multibyte read.
Data access time after SCLK rising edge following a write to the
Communications Register.
Bus relinquish time after falling edge of SCLK.
t
t
10
4
30
μ
s (min)
ns (min)
t
124
100
10
100
10
ns (max)
ns (min)
ns (max)
ns (min)
t
134
Bus relinquish time after rising edge of
CS
.
NOTES
1
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to
90%) and timed from a voltage level of 1.6 V.
2
See timing diagram below and Serial Interface section of this data sheet.
3
Measured with the load circuit in
Load Circuit for Timing Specifications
and defined as the time required for the output to cross 0.8 V or 2.4 V.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Load Circuit for Timing Specifications. The measured
number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics
is the true bus relinquish time of the part and is independent of the bus loading.
Specifications subject to change without notice.
200 A
1.6mA
I
OL
C
L
50pF
TO
OUTPUT
PIN
2.1V
I
OH
Figure 1. Load Circuit for Timing Specifications
t
5
t
4
CS
SCLK
DIN
A4
A3
A2
A1
A0
DB7
MOST SIGNIFICANT BYTE
1
DB0
DB7
DB0
LEAST SIGNIFICANT BYTE
0
0
COMMAND BYTE
t
1
t
2
t
3
t
6
t
7
t
8
Figure 2. Serial Write Timing
CS
SCLK
DIN
A4
A3
A2
A1
A0
0
0
0
t
1
t
10
DOUT
DB7
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
COMMAND BYTE
DB0
DB7
DB0
t
13
t
12
t
9
t
11
t
11
Figure 3. Serial Read Timing
(AV
= DV
= 5 V 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz
XTAL, T
MIN
to T
MAX
= –40 C to +85 C, unless otherwise noted.)
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