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參數(shù)資料
| 型號： | EVAL-ADE7756EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Active Energy Metering IC with Serial Interface |
| 中文描述： | 有源電能計量IC串行接口 |
| 文件頁數(shù)： | 28/32頁 |
| 文件大?。?/td> | 347K |
| 代理商： | EVAL-ADE7756EB |
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REV. 0
ADE7756
–28–
Table IV. Register List
No. of
Bits
Address
Name
R/W
Default
Description
00h
01h
Not Used
WAVEFORM
No Operation.
The Waveform register is a 24 bit read-only register. This register
contains the sampled waveform data from either Channel 1, Channel 2
or the Active Power signal. The data source is selected by data bits 14
and 13 in the Mode Register—see Channel 1 and 2 Sampling sections.
The Active Energy Register. Active Power is accumulated (Integrated)
over time in this 40-bit, read-only register. The energy register can hold a
minimum of 6 seconds of Active Energy information with full-scale
analog inputs before it overflows—see Energy Calculation section.
Same as the Active Energy register except that the register is reset to
zero following a read operation
The Interrupt Status Register. This is an 8-bit read-only register. The
Status Register contains information regarding the source of ADE7756
interrupts—see Interrupts section.
Same as the Interrupt Status register except that the register contents
are reset to zero (all flags cleared) after a read operation.
The Mode Register. This is a 16-bit register through which most of the
ADE7756 functionality is accessed. Signal sample rates, filter enabling
and calibration modes are selected by writing to this register. The contents
may be read at any time—see Mode Register section.
The Frequency Divider Register. This is a 12-bit read/write register.
The output frequency on the CF pin is adjusted by writing to this
register—see Energy to Frequency Conversion section
.
Channel 1 Offset Adjust. Writing to this 6-bit register allows any off-
sets on Channel 1 to be removed—see Analog Inputs section.
Channel 2 Offset Adjust. Writing to this 6-bit register allows any off-
sets on Channel 2 to be removed—see Analog Inputs section.
PGA Gain Adjust. This 8-bit register is used to adjust the gain selec-
tion for the PGA in Channel 1 and Channel 2—Analog Inputs section.
Active Power Gain Adjust. This is a 12-bit register. The Active Power
calculation can be calibrated by writing to this register. The calibration
range is
±
50% of the nominal full scale active power. The resolution
of the gain adjust is 0.0244%/LSB—see Channel 1 ADC Gain
Adjust section.
Phase Calibration Register. The phase relationship between Channel 1
and Channel 2 can be adjusted by writing to this 6-bit register. The
adjustment range is approximately
±
3.1
°
at 60 Hz in 0.097
°
steps—see
Phase Compensation section.
Active Power Offset Correction. This 12-bit register allows small off-
sets in the Active Power Calculation to be removed—see Active Power
Calculation section.
Zero-Cross Time Out. If no zero crossings are detected on Channel 2
within a time period specified by this 12-bit register, the interrupt
request line (
IRQ
) will be activated. The maximum time-out period is
0.15 second—see Zero Crossing Detection section.
Sag Line Cycle Register. This 8-bit register specifies the number of
consecutive half line cycles the signal on Channel 2 must be below
SAGLVL before the SAG output is activated—see
V
oltage Sag Detec-
tion section. It is also used during calibration mode to set the number
of line cycles Active power is accumulated for Energy calibration—see
Energy Calibration section.
R
24
0h
02h
AENERGY
R
40
0h
03h
RSTENERGY
R
40
0h
04h
STATUS
R
8
0h
05h
RSTSTATUS
R
8
0h
06h
MODE
R/W
16
000Ch
07h
CFDIV
R/W
12
3Fh
08h
CH1OS
R/W
6
0h
09h
CH2OS
R/W
6
0h
0Ah
GAIN
R/W
8
0h
0Bh
APGAIN
R/W
12
0h
0Ch
PHCAL
R/W
6
0h
0Dh
APOS
R/W
12
8h
0Eh
ZXTOUT
R/W
12
FFFFh
0Fh
SAGCYC
R/W
8
FFh
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