參數(shù)資料
型號: EVAL-AD7940CBZ
廠商: Analog Devices Inc
文件頁數(shù): 7/20頁
文件大?。?/td> 0K
描述: BOARD EVALUATION AD7940
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 1
位數(shù): 14
采樣率(每秒): 100k
數(shù)據(jù)接口: 串行
輸入范圍: 0 ~ Vdd
在以下條件下的電源(標(biāo)準(zhǔn)): 17mW @ 100kSPS & 5V
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD7940
已供物品:
相關(guān)產(chǎn)品: AD7940BRJZ-REEL7DKR-ND - IC ADC 14BIT 100KSPS SOT-23-6
AD7940BRJZ-REEL7CT-ND - IC ADC 14BIT 100KSPS SOT-23-6
AD7940BRJZ-REEL7TR-ND - IC ADC 14BIT 100KSPS SOT-23-6
AD7940BRM-ND - IC ADC 14BIT UNIPOLAR 8-MSOP
AD7940BRM-REEL7TR-ND - IC ADC 14BIT UNIPOLAR 8-MSOP
AD7940
Rev. A | Page 15 of 20
POWER VS. THROUGHPUT RATE
By using the power-down mode on the AD7940 when not
converting, the average power consumption of the ADC
decreases at lower throughput rates. Figure 19 shows how as the
throughput rate is reduced, the part remains in its shutdown
state longer, and the average power consumption over time
drops accordingly.
For example, if the AD7940 is operated in a continuous
sampling mode, with a throughput rate of 10 kSPS and an SCLK
of 2.5 MHz (VDD = 3.6 V), and the device is placed in power-
down mode between conversions, the power consumption is
calculated as follows. The maximum power dissipation during
normal operation is 6.84 mW (VDD = 3.6 V). If the power-up
time from power-down is 1 s, and the remaining conversion
time is 6.4 s, (using a 16 SCLK transfer), then the AD7940 can
be said to dissipate 6.84 mW for 7.4 s during each conversion
cycle. With a throughput rate of 10 kSPS, the cycle time is 100
s. For the remainder of the conversion cycle, 92.6 s, the part
remains in power-down mode. The AD7940 can be said to
dissipate 1.08 W for the remaining 92.6 s of the conversion
cycle. Therefore, with a throughput rate of 10 kSPS, the average
power dissipated during each cycle is
(7.4/100) × (6.84 mW) + (92.6/100) × (1.08 W) = 0.51 mW
Figure 19 shows the power dissipation versus the throughput
rate when using the power-down mode with 3.6 V supplies and
a 2.5 MHz SCLK.
03305-0-012
POWER
(mW)
0.01
0
5
10
15
20
25
THROUGHPUT (kSPS)
30
35
40
45
50
0.1
1
10
VDD = 3.6V
FSCLK = 2.5MHz
Figure 19. Power vs. Throughput Using Power-Down Mode at 3.6 V
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