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參數(shù)資料
| 型號： | EVAL-AD7934CB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | 4-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer |
| 中文描述： | 4通道，1.5 MSPS的12位和10位并行ADC的一個序列 |
| 文件頁數(shù)： | 28/32頁 |
| 文件大?。?/td> | 1253K |
| 代理商： | EVAL-AD7934CB |
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AD7933/AD7934
Preliminary Technical Data
POWER VS. THROUGHPUT RATE
A big advantage of powering the ADC down after a conversion
is that the power consumption of the part is significantly
reduced at lower throughput rates. When using the different
power modes, the AD7933/AD7934 is only powered up for the
duration of the conversion. Therefore, the average power
consumption per cycle is significantly reduced. F
show plots of the power versus the throughput when
operating in auto shutdown and auto standby modes.
and
igure 42
Figure 42. Power vs. Throughput in Auto Shutdown Mode
Figure 43
Figure 43. Power vs. Throughput in Auto Standby Mode
MICROPROCESSOR INTERFACING
AD7933/AD7934 to ADSP-21xx Interface
Figure 44
shows the AD7933/AD7934 interfaced to the ADSP-
21xx series of DSPs as a memory mapped device. A single wait
state may be necessary to interface the AD7933/AD7934 to the
ADSP-21xx, depending on the clock speed of the DSP. The wait
state can be programmed via the data memory wait state
control register of the ADSP-21xx (see the ADSP-21xx family
User’s Manual for details). The following instruction reads from
the AD7933/AD7934:
Figure 44. Interfacing to the ADSP-21xx
AD7933/AD7934 to ADSP-21065L Interface
Figure 45
shows a typical interface between the
AD7933/AD7934 and the ADSP-21065L SHARC processor.
This interface is an example of one of three DMA handshake
modes. The MS
x
control line is actually three memory select
lines. Internal ADDR
25–24
are decoded into MS
3-0
, these lines are
then asserted as chip selects. The DMAR
1
(DMA request 1) is
used in this setup as the interrupt to signal the end of the
conversion. The rest of the interface is standard handshaking
operation.
MR = DM (ADC)
where ADC is the address of the AD7933/AD7934.
AD7933/
AD7934*
ADSP-21xx*
WR
RD
DB0 TO DB11
D0 TO D23
A0 TO A15
DMS
IRQ2
BUSY
CS
CONVST
OPTIONAL
WR
RD
*ADDITIONAL PINS OMITTED FOR CLARITY
ADDRESS BUS
DATA BUS
ADDRESS
DECODER
0
Figure 45. Interfacing to the ADSP-21065L
AD7933/
AD7934*
ADSP-21065L*
WR
DB0 TO DB11
D0 TO D31
ADDR
0
TO ADDR
23
MS
X
DMAR
1
BUSY
CS
CONVST
OPTIONAL
WR
RD
RD
*ADDITIONAL PINS OMITTED FOR CLARITY
ADDRESS BUS
ADDRESS BUS
DATA BUS
ADDRESS
LATCH
ADDRESS
DECODER
0
Rev. PrG | Page 28 of 32
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