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參數資料
| 型號： | EVAL-AD9833EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | +2.5 V to +5.5 V, 25 MHz Low Power CMOS Complete DDS |
| 中文描述： | 2.5 V至5.5 V，25 MHz低功耗CMOS完整的DDS |
| 文件頁數： | 1/18頁 |
| 文件大?。?/td> | 210K |
| 代理商： | EVAL-AD9833EB |
+2.5 V to +5.5 V, 25 MHz Low Power
CMOS Complete DDS
Preliminary
Technical
Data
AD9833
FEATURES
+2.3 V to +5.5 V Power Supply
25 MHz Speed
Tiny 10-Pin
μ
SOIC Package
Serial Loading
Sinusoidal/Triangular DAC Output
Power-Down Option
Narrowband SFDR > 72 dB
20 mW Power Consumption at 3 V
APPLICATIONS
Digital Modulation
Portable Equipment
Test Equipment
DDS Tuning
Serial Interface
&
Control Logic
SCLK
SDATA
FSYNC
Control Register
PHASE1 REG
PHASE0 REG
MUX
SIN
ROM
Σ
10-Bit DAC
COMP
FullScale
Control
MUX
FREQ0 REG
MCLK
FREQ1 REG
12
On-Board
Reference
AGND
DGND
VDD
AD9833
Phase
Accumulator
(28 Bit)
Regulator
CAP/2.5V
2.5V
AVDD/
DVDD
VOUT
MUX
DIV BY
2
MSB
MUX
R
200
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
This low power DDS device is a numerically controlled
oscillator employing a phase accumulator, a SIN ROM
and a 10-bit D/A converter integrated on a single
CMOS chip. Clock rates up to 25 MHz are supported
with a power supply from +2.3 V to +5.5 V.
Capability for phase modulation and frequency modula-
tion is provided. Frequency accuracy can be controlled to
one part in 0.25 billion. Modulation is effected by loading
registers through the serial interface.
The AD9833 offers a variety of output waveforms from
the VOUT pin. The SIN ROM can be bypassed so that a
linear up/down ramp is output from the DAC. If the SIN
ROM is not by-passed, a sinusoidal output is available.
Also, if a clock output is required, the MSB of the DAC
data can be output.
The digital section is internally operated at +2.5 V, irre-
spective of the value of VDD, by an on board regulator
which steps down VDD to +2.5 V, when VDD exceeds
+2.5 V.
The AD9833 has a power-down function (SLEEP). This
allows sections of the device which are not being used to
be powered down, thus minimising the current consump-
tion of the part e.g the DAC can be powered down when a
clock output is being generated.
The AD9833 is available in a 10-pin
μ
SOIC package.
PRELIMINARY TECHNICAL DATA
REV PrG 02/02
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
Analog Devices, Inc., 2002
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