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參數(shù)資料
| 型號(hào)： | EVAL-AD7858CB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADC |
| 中文描述： | 3 V至5 V單電源，200 kSPS的8通道，12位采樣ADC |
| 文件頁(yè)數(shù)： | 5/32頁(yè) |
| 文件大?。?/td> | 315K |
| 代理商： | EVAL-AD7858CB |
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AD7858/AD7858L
REV. B
–5–
TYPICAL TIMING DIAGRAMS
Figures 2 and 3 show typical read and write timing diagrams for
serial Interface Mode 2. The reading and writing occurs after
conversion in Figure 2, and during conversion in Figure 3. To
attain the maximum sample rate of 100 kHz (AD7858L) or
200 kHz (AD7858), reading and writing must be performed
during conversion as in Figure 3. At least 400 ns acquisition
time must be allowed (the time from the falling edge of BUSY
to the next rising edge of
CONVST
) before the next conversion
begins to ensure that the part is settled to the 12-bit level. If the
user does not want to provide the
CONVST
signal, the conver-
sion can be initiated in software by writing to the control register.
1.6mA
200 A
I
OL
I
OH
TO
OUTPUT
PIN
C
L
100pF
+2.1V
Figure 1. Load Circuit for Digital Output Timing
Specifications
t
CONVERT
= 4.6 s MAX, 10 s MAX FOR L VERSION
t
1
= 100ns MIN,
t
4
= 50/90ns MAX 5V/3V,
t
7
= 40/60ns MIN 5V/3V
t
1
t
CONVERT
t
3
t
4
t
6
t
2
t
6
t
9
t
10
t
11
t
12
t
7
t
8
THREE-STATE
1
5
6
16
DB15
DB11
DB0
DB15
DB11
DB0
CONVST
(I/P)
BUSY (O/P)
SYNC
(I/P)
SCLK (I/P)
DOUT (O/P)
DIN (I/P)
THREE-
STATE
Figure 2. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing After Conversion)
t
CONVERT
= 4.6 s MAX, 10 s MAX FOR L VERSION
t
1
= 100ns MIN,
t
4
= 50/90ns MAX 5V/3V,
t
7
= 40/60ns MIN 5V/3V
t
1
t
CONVERT
t
3
t
4
t
6
t
2
t
6
t
9
t
10
t
11
t
12
t
7
t
8
THREE-STATE
1
5
6
16
DB15
DB11
DB0
DB15
DB11
DB0
CONVST
(I/P)
BUSY (O/P)
SYNC
(I/P)
SCLK (I/P)
DOUT (O/P)
DIN (I/P)
THREE-
STATE
Figure 3. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing During Conversion)
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