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參數(shù)資料
| 型號： | EVAL-AD7858CB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADC |
| 中文描述： | 3 V至5 V單電源，200 kSPS的8通道，12位采樣ADC |
| 文件頁數(shù)： | 26/32頁 |
| 文件大?。?/td> | 315K |
| 代理商： | EVAL-AD7858CB |
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REV. B
–26–
AD7858/AD7858L
CONFIGURING THE AD7858/AD7858L
The AD7858/AD7858L contains 14 on-chip registers which can
be accessed via the serial interface. In the majority of applications it
will not be necessary to access all of these registers. Here the
CLKIN signal is applied directly after power-on; the CLKIN
signal must be present to allow the part to perform a calibration.
This automatic calibration will be completed approximately 32 ms
after the AD7858 has powered up (4 MHz CLK).
For accessing the on-chip registers it is necessary to write to the
part. To change the channel from the default channel setting
the user will be required to write to the part. To enable Serial
Interface Mode 1 the user must also write to the part. Figure 34
and 35 outline flowcharts of how to configure the AD7858/
AD7858L Serial Interface Modes 1 and 2 respectively. The
continuous loops on all diagrams indicate the sequence for more
than one conversion. The options of using a hardware (pulsing
the
CONVST
pin) or software (setting the CONVST bit to 1)
conversion start, and reading/writing during or after conversion
are shown in Figures 34 and 35. If the
CONVST
pin is never
used then it should be tied to DV
DD
permanently. Where refer-
ence is made to the BUSY bit equal to a Logic 0, to indicate the
end of conversion, the user in this case would poll the BUSY bit
in the status register.
Interface Mode 1 Configuration
Figure 34 shows the flowchart for configuring the part in Inter-
face Mode 1. This mode of operation can only be enabled by
writing to the control register and setting the 2/
3
MODE bit.
Reading and writing cannot take place simultaneously in this
mode as the DIN pin is used for both reading and writing.
INITIATE
CONVERSION
IN
SOFTWARE
START
POWER-ON, APPLY CLKIN SIGNAL,
WAIT FOR AUTOMATIC CALIBRATION
APPLY
SYNC
(IF REQUIRED), SCLK,
WRITE TO CONTROL REGISTER
SETTING CHANNEL AND TWO-WIRE MODE
PULSE
CONVST
PIN
WAIT FOR BUSY SIGNAL TO GO LOW
OR
WAIT FOR BUSY BIT = 0
NO
1
SERIAL
INTERFACE
MODE
APPLY
SYNC
(IF REQUIRED), SCLK, WRITE
TO CONTROL REGISTER SETTING CHANNEL
TWO-WIRE MODE
READ
DATA
DURING
CONVERSION
NO
YES
YES
APPLY
SYNC
(IF REQUIRED), SCLK, READ
CURRENT CONVERSION RESULT ON DIN PIN
APPLY
SYNC
(IF REQUIRED), SCLK, READ
PREVIOUS CONVERSION RESULT ON DIN PIN
WAIT APPROX. 200ns AFTER
CONVST
RISING EDGE OR AFTER END
OF CONTROL REGISTER WRITE
WRITE
TO CONTROL REGISTER SETTING CONVST
BIT TO 1 (SEE NOTE)
NOTE:
TWO SEPARATE WRITES ARE REQUIRED TO SET A NEW CHANNEL ADDRESS AND INITIATE A
CONVERSION ON THAT NEW CHANNEL IN SOFTWARE AS THE ACQUISITION TIME (2
t
)
MUST ELAPSE BEFORE THE CONVERSION BEGINS. IF BOTH COMMANDS ARE ISSUED IN THE ONE
WRITE THE RESULT OF THIS CONVERSION SHOULD BE DISCARDED AND THE NEXT
CONVERSION ON THAT SAME CHANNEL WILL PROVIDE CORRECT RESULTS.
Figure 34. Flowchart for Setting Up, Reading, and Writing in Interface Mode 1
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