
REV. A
–2–
AD7851–SPECIFICATIONS
1, 2
A Grade: f
CLKIN
= 7 MHz (–40
8
C to +85
8
C), f
SAMPLE
= 333kHz; K Grade: f
CLKIN
= 6 MHz
238 kHz; (AV
DD
= DV
DD
= +5.0 V
6
5%,
REF
IN
/REF
OUT
= 4.096 V External Reference; SLEEP
= Logic Hgh; T
A
= T
MN
to T
MAX
, unless otherwse noted)
Parameter
A
1
K
1
(0
8
C to +85
8
C), f
SAMPLE
= 285 kHz; A and K Grade: f
CLKIN
= 5 MHz (to +125
8
C), f
SAMPLE
=
Units
T est Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion Ratio
3
(SNR)
77
78
dB min
T ypically SNR is 79.5 dB
V
IN
= 10 kHz, Sine Wave, f
SAMPLE
= 333 kHz
V
IN
= 10 kHz, Sine Wave, f
SAMPLE
= 333 kHz,
T ypically –96 dB
V
IN
= 10 kHz, f
SAMPLE
= 333 kHz
T otal Harmonic Distortion (T HD)
–86
–86
dB max
Peak Harmonic or Spurious Noise
Intermodulation Distortion (IMD)
Second Order T erms
T hird Order T erms
Full Power Bandwidth
–87
–87
dB max
–86
–86
20
–90
–90
20
dB typ
dB typ
MHz typ
fa = 9.983 kHz, fb = 10.05 kHz, f
SAMPLE
= 333 kHz
fa = 9.983 kHz, fb = 10.05 kHz, f
SAMPLE
= 333 kHz
@ 3 dB
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Unipolar Offset Error
Positive Full-Scale Error
Negative Full-Scale Error
Bipolar Zero Error
14
±
2
±
2
±
10
±
10
±
10
±
1
14
±
1
±
1
±
10
±
10
±
10
±
1
Bits
LSB max
LSB max
LSB max
LSB max
LSB typ
LSB typ
Guaranteed No Missed Codes to 14 Bits
Review: “Adjusting the Offset Calibration
Register” in the “Calibration Registers” section
of the data sheet.
ANALOG INPUT
Input Voltage Ranges
0 V to V
REF
0 V to V
REF
Volts
i.e., AIN(+) – AIN(–) = 0 V to V
REF
, AIN(–) can be
biased up but AIN(+) cannot go below AIN(–).
i.e., AIN(+) – AIN(–) = –V
REF
/2 to +V
REF
/2, AIN(–)
should be biased up and AIN(+) can go below
AIN(–) but cannot go below 0 V.
±
V
REF
/2
±
V
REF
/2
Volts
Leakage Current
Input Capacitance
±
1
20
±
1
20
μ
A max
pF typ
REFERENCE INPUT /OUT PUT
REF
IN
Input Voltage Range
Input Impedance
REF
OUT
Output Voltage
REF
OUT
T empco
4/V
DD
150
3.696/4.496 3.696/4.496
50
4/V
DD
150
V min/max
k
typ
V min/max
ppm/
°
C typ
Functional from 1.2 V
Resistor Connected to Internal Reference Node
50
LOGIC INPUT S
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN5
V
DD
– 1.0
0.4
±
10
10
V
DD
– 1.0
0.4
±
10
10
V min
V max
μ
A max
pF max
V
IN
= 0 V or V
DD
LOGIC OUT PUT S
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
5
Output Coding
V
DD
– 0.4
0.4
±
10
10
Straight (Natural) Binary
2s Complement
V
DD
– 0.4
0.4
±
10
10
V min
V max
μ
A max
pF max
I
SOURCE
= 200
μ
A
I
SINK
= 0.8 mA
Unipolar Input Range
Bipolar Input Range
CONVERSION RAT E
Conversion T ime
Conversion + T /H Acquisition T ime
2.78
3.0
3.25
3.5
μ
s max
μ
s max
19.5 CLK IN Cycles
21 CLK IN Cycles T hroughput Rate