參數(shù)資料
型號(hào)： EVAL-AD7718EB
廠商： Analog Devices, Inc.
英文描述： 8-/10-Channel, Low Voltage, Low Power, ADCs
中文描述： 8-/10-Channel，低電壓，低功耗，ADC的
文件頁(yè)數(shù)： 27/44頁(yè)
文件大小： 339K
代理商： EVAL-AD7718EB
REV. 0
AD7708/AD7718
–27–
Mode Register (A3, A2, A1, A0 = 0, 0, 0, 1; Power-On-Reset = 00Hex)
The Mode Register is an 8-bit register from which data can be read or to which data can be written. This register configures the
operating modes of the AD7708/AD7718. Table XV outlines the bit designations for the Mode Register. MR7 through MR0 indi-
cate the bit location, MR denoting the bits are in the Mode Register. MR7 denotes the first bit of the data stream. The number in
brackets indicates the power-on/reset default status of that bit.
7
R
M
6
R
M
5
R
M
4
R
M
3
R
M
2
R
M
1
R
M
0
R
M
P
O
H
C
)
0
(
)
0
(
F
U
B
G
E
N
)
0
(
L
E
S
F
E
R
)
0
(
N
O
C
H
C
)
0
(
D
P
C
S
O
)
0
(
2
D
M
)
0
(
1
D
M
)
0
(
0
D
M
Table XV. Mode Register Bit Designations
Bit
Location
MR7
Bit
Mnemonic
CHOP
Description
If this bit is
cleared,
chopping is enabled. When this bit is
set
chopping is disabled. The default is for
chop enabled.
This bit controls the operation of the input buffer on the AINCOM input when a channel is config-
ured for pseudo-differential mode of operation. If
cleared,
the analog negative input (AINCOM) is
unbuffered allowing it to be tied to AGND in single-ended input configuration. If this bit is
set
the
analog negative input (AINCOM) is buffered, placing a restriction on its common-mode input range.
If this bit is
cleared
, the reference selected is REFIN1(+) and REFIN1(–) for the active channel. If
this bit is
set
, the reference selected is REFIN2(+) and REFIN2(–) for the active channel. The con-
tents of the CHCON bit overrides the REFSEL bit. If the ADC is configured in five fully-differential
or 10 pseudo-differential input channel mode, the REFSEL bit setting is irrelevant as only one
reference input is available.
V
REF
Select
implemented using the REFSEL bit enables the user to
perform both absolute and ratiometric measurements.
When
cleared
the device is configured as an 8-input channel converter, configured as eight pseudo-
differential input channels with respect to AINCOM or four differential input arrangements
with two reference input selection options. When
set
the device is configured as a 10 pseudo-
differential input or a five differential input channel arrangement with a single reference
input option.
Oscillator Power-Down Bit.
If this bit is
set
, placing the AD7708/AD7718 in standby mode will stop the crystal oscillator reducing
the power drawn by these parts to a minimum. The oscillator will require 300 ms to begin oscillating
when the ADC is taken out of standby mode. If this bit is
cleared
, the oscillator is not shut off when
the ADC is put into standby mode and will not require the 300 ms start-up time when the ADC is
taken out of standby.
ADC Mode Bits.
These bits select the operational mode of the ADC as follows:
MR6
NEGBUF
MR5
REFSEL
MR4
CHCON
MR3
OSCPD
MR2–MR0
MD2–MD0
MD2
0
0
MD1
0
0
MD0
0
1
Power-Down Mode (Power-On Default)
Idle Mode
In Idle Mode the ADC filter and modulator are held in a reset state although the modulator clocks
are still provided.
Single Conversion Mode
In Single Conversion Mode, a single conversion is performed on the enabled channels. On comple-
tion of the conversion the ADC data registers are updated, the relevant flags in the STATUS register
are written, and idle mode is reentered with the MD2–MD0 being written accordingly to 001.
Continuous Conversion
In continuous conversion mode, the ADC data registers are regularly updated at the selected update
rate (see Filter register).
Internal Zero-Scale Calibration
Internal short automatically connected to the enabled channel(s)
Internal Full-Scale Calibration
External V
REF
is connected automatically to the ADC input for this calibration.
System Zero-Scale Calibration
User should connect system zero-scale input to the channel input pins as selected by CH3–CH0 bits
in the control registers.
System Full-Scale Calibration
User should connect system full-scale input to the channel input pins as selected by CH3–CH0 bits
in the control registers.
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
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