
- 2 -
Rev. 0
EVAL-AD7707EB
L INK A ND SWIT C H OPT IONS
T here are ten link options which must be set for the required operating setup before using the evaluation board. T he functions
of these link options are outlined below.
L ink No.
L K 1
F unction
T his option selects the master clock source for the AD7707. T he master clock is generated by the on-board crystal
or from an external source via SK T 11. T his is a double link and both links must be moved together for the correct
operation of the evaluation board.
With both links in position "A", the external clock option is selected and an external clock applied to SK T 11 is
routed to the MCLK IN pin of the AD7707.
With both links in position "B", the on-board crystal is selected to provide the master clock to the AD7707.
T his link is used to select the on-board reference.
With this link in position "A", the AD780 is selected as the on-board reference. T his provides a 2.5V reference
which is suitable for the AD7707 operating at +5V.
With this link in position "B", the AD589 is selected as the on-board reference. T his provides a 1.23V reference
which is suitable for the AD7707 operating at +3V.
T his link is used to select the reference source for the REFIN(-) input of the AD7707.
With this link in position"A", the REFIN(-) pin is connected directly to AGND.
With this link in position "B", the REFIN(-) pin is connected to SK T 10. An external voltage applied to SK T 10
can now be used as the REFIN(-) for the AD7707.
T his link is used to select the reference source for the REFIN(+) input of the AD7707.
With LK 4 in position "A", the REFIN(+) pin is connected to the output of the on-board reference.
With LK 4 in position "B", the REFIN(+) pin is connected to SK T 9. An external voltage applied to SK T 9 can
now be used as the REFIN(+) for the AD7707.
T his link is in series with the AIN1 input of the AD7707.
With this link in place, an analog input signal applied to SK T 3 is routed directly to the AIN1 pin of the AD7707.
T his link may be removed so that the user can add signal conditioning circuitry if required.
T his link is in series with the AIN2 input of the AD7707.
With this link in place, an analog input signal applied to SK T 4 is routed directly to the AIN2 pin of the AD7707.
T his link may be removed so that the user can add signal conditioning circuitry if required.
T his link is in series with the AIN3 input of the AD7707.
With this link in place, an analog input signal applied to SK T 5 is routed directly to the AIN3 pin of the AD7707.
T his link may be removed so that the user can add signal conditioning circuitry if required.
T his link is used to select the common input for low level input channels (AIN1 and AIN2).
With this link in position "A", the LCOM input is tied to AGND.
With this link in position "B", the LCOM input is tied to VREF.
With this link in position "C", the LCOM input is set to a voltage applied to SK T 6.
T his link is connected to the HBIAS pin. It used to signal condition the high level input channel (AIN3).
With this link in positoin "A", the HBIAS pin is tied to the REFIN+ pin of te AD7707.
With this link in position "B", a voltage applied to SK T 7 is applied to the HBIAS pin.
T his link is connected to the HCOM pin of the AD7707. It stes the common input voltage for the high level input
channel (AIN3).
With this link in position "A", the HCOM input is tied to AGND.
With this link in position "B", the HCOM input is tied to VREF.
With this link in position "C", the HCOM input is set to a voltage applied to SK T 8.
L K 2
L K 3
L K 4
L K 5
L K 6
L K 7
L K 8
L K 9
L K 10