參數(shù)資料
型號(hào)： EVAL-AD7327SDZ
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 22/37頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR AD7327SDZ
標(biāo)準(zhǔn)包裝： 1
系列： *
AD7327
Rev. B | Page 28 of 36
MODES OF OPERATION
The AD7327 has several modes of operation that are designed
to provide flexible power management options. These options
can be chosen to optimize the power dissipation/throughput
rate ratio for different application requirements. The mode of
operation of the AD7327 is controlled by the power management
bits, Bit PM1 and Bit PM0, in the control register as shown in
Table 11. The default mode is normal mode, where all internal
circuitry is fully powered up.
NORMAL MODE
(PM1 = PM0 = 0)
This mode is intended for the fastest throughput rate performance
with the AD7327 being fully powered up at all times. Figure 48
shows the general operation of the AD7327 in normal mode.
The conversion is initiated on the falling edge of CS, and the
track-and-hold section enters hold mode, as described in the
Serial Interface section. Data on the DIN line during the 16 SCLK
transfer is loaded into one of the on-chip registers if the write bit
is set. The register is selected by programming the register select
bits (see Table 8).
116
3 CHANNEL I.D. BITS, SIGN BIT + CONVERSION RESULT
DATA INTO CONTROL/SEQUENCE/RANGE1/RANGE2
REGISTER
SCLK
CS
DOUT
DIN
0
5
401-
035
Figure 48. Normal Mode
The AD7327 remains fully powered up at the end of the
conversion if both PM1 and PM0 contain 0 in the control
register.
To complete the conversion and access the conversion result,
16 serial clock cycles are required. At the end of the conversion,
CS can idle either high or low until the next conversion.
Once the data transfer is complete, another conversion can be
initiated after the quiet time, tQUIET, has elapsed.
FULL SHUTDOWN MODE
(PM1 = PM0 = 1)
In this mode, all internal circuitry on the AD7327 is powered
down. The part retains information in the registers during full
shutdown. The AD7327 remains in full shutdown mode until
the power management bits, Bit PM1 and Bit PM0, in the
control register are changed.
A write to the control register with PM1 = 1 and PM0 = 1 places
the part into full shutdown mode. The AD7327 enters full shut-
down mode on the 15th SCLK rising edge once the control register
is updated.
If a write to the control register occurs while the part is in full
shutdown mode with the power management bits, Bit PM1 and
Bit PM0, set to 0 (normal mode), the part begins to power up
on the 15th SCLK rising edge once the control register is updated.
Figure 49 shows how the AD7327 is configured to exit full
shutdown mode. To ensure the AD7327 is fully powered up,
tPOWER-UP should elapse before the next CS falling edge.
CS
116
1
16
SCLK
SDATA
DIN
INVALID DATA
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DATA INTO CONTROL REGISTER
tPOWER-UP
THE PART IS FULLY POWERED UP
ONCE
tPOWER-UP HAS ELAPSED
CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS,
PM1 = 0, PM0 = 0
TO KEEP THE PART IN NORMAL MODE, LOAD PM1 = PM0 = 0
IN CONTROL REGISTER
PART IS IN FULL
SHUTDOWN
PART BEGINS TO POWER UP ON THE 15TH
SCLK RISING EDGE AS PM1 = PM0 = 0
0
5401-
041
Figure 49. Exiting Full Shutdown Mode
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