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| 型號： | EVAL-AD7327SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD7327SDZ |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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AD7327
Rev. B | Page 18 of 36
D
VDD
C2
R1
VIN+
VSS
C1
D
VDD
C2
R1
VIN–
VSS
C1
054
01-
024
Figure 30. Equivalent Analog Input Circuit (Differential)
Care should be taken to ensure that the analog input does not
exceed the VDD and VSS supply rails by more than 300 mV.
Exceeding this value causes the diodes to become forward
biased and to start conducting into either the VDD supply rail or
VSS supply rail. These diodes can conduct up to 10 mA without
causing irreversible damage to the part.
In Figure 29 and Figure 30, Capacitor C1 is typically 4 pF and
can primarily be attributed to pin capacitance. Resistor R1 is a
lumped component made up of the on resistance of the input
multiplexer and the track-and-hold switch. Capacitor C2 is the
sampling capacitor; its capacitance varies depending on the
analog input range selected (see the Specifications section).
Track-and-Hold Section
The track-and-hold on the analog input of the AD7327 allows
the ADC to accurately convert an input sine wave of full-scale
amplitude to 13-bit accuracy. The input bandwidth of the track-
and-hold is greater than the Nyquist rate of the ADC. The
AD7327 can handle frequencies up to 22 MHz.
The track-and-hold enters its tracking mode on the 14th SCLK
rising edge after the CS falling edge. The time required to
acquire an input signal depends on how quickly the sampling
capacitor is charged. With 0 source impedance, 305 ns is sufficient
to acquire the signal to the 13-bit level. The acquisition time
required is calculated using the following formula:
tACQ = 10 × ((RSOURCE + R) × C)
where C is the sampling capacitance, and R is the resistance
seen by the track-and-hold amplifier looking back on the input.
For the AD7327, the value of R includes the on resistance of the
input multiplexer and is typically 300 Ω. RSOURCE should include
any extra source impedance on the analog input.
running the AD7327 at a throughput rate of 500 kSPS with a
10 MHz SCLK signal, the ADC has approximately
1.5 SCLK + t8 + tQUIET
to acquire the analog input signal. The ADC goes back into
hold mode on the CS falling edge.
As the VDD/VSS supply voltage is reduced, the on resistance of
the input multiplexer increases. Therefore, based on the equation
for tACQ, it is necessary to increase the amount of acquisition time
provided to the AD7327, and, therefore, decrease the overall
are reduced, the specified THD performance degrades slightly.
If the throughput rate is reduced when operating with the
minimum VDD and VSS supplies, the specified THD performance
is maintained.
519
±VDD/VSS SUPPLIES (V)
TH
D
(
dB
)
7
9
11
13
15
17
0
5401-
051
–95
–75
–80
–85
–90
500kSPS
VCC =VDRIVE =5V
INTERNAL REFERENCE
TA =25°C
FIN =10kHz
±5V RANGE
SE MODE
Figure 31. THD vs. ±VDD/VSS Supply Voltage at 500 kSPS
Unlike other bipolar ADCs, the AD7327 does not have a
resistive analog input structure. On the AD7327, the bipolar
analog signal is sampled directly onto the sampling capacitor.
This gives the AD7327 high analog input impedance. An
approximation for the analog input impedance can be
calculated from the following formula:
Z = 1/(fS × CS)
where fS is the sampling frequency, and CS is the sampling
capacitor value.
CS depends on the analog input range chosen (see the
Specifications section). When operating at 500 kSPS, the analog
input impedance is typically 145 kΩ for the ±10 V range. As the
sampling frequency is reduced, the analog input impedance
further increases. As the analog input impedance increases, the
current required to drive the analog input, therefore, decreases.
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