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| 型號(hào)： | EVAL-AD5663REB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference |
| 中文描述： | 5分之/ C對(duì)芯片參考雙12-/14-/16-Bit nanoDAC系列 |
| 文件頁(yè)數(shù)： | 21/28頁(yè) |
| 文件大?。?/td> | 1176K |
| 代理商： | EVAL-AD5663REB |
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AD5623R/AD5643R/AD5663R
At this stage, the SYNC line can be kept low or be brought high.
In either case, it must be brought high for a minimum of 15 ns
before the next write sequence, so that a falling edge of SYNC
can initiate the next write sequence.
Rev. A | Page 21 of 28
Because the SYNC buffer draws more current when V
IN
= 2 V
than it does when V
IN
= 0.8 V SYNC should be idled low between
write sequences for even lower power operation. As mentioned
previously, it must, however, be brought high again just before
the next write sequence.
INPUT SHIFT REGISTER
The input shift register is 24 bits wide (see Figure 52). The first
two bits are don’t cares. The next three are Command Bit C2 to
Command Bit C0 (see Table 8), followed by the 3-bit DAC
Address A2 to DAC Address A0 (see Table 9), and, finally, the
16-, 14-, and 12-bit data-word.
The data-word comprises the 16-, 14-, and 12-bit input codes,
followed by zero, two, or four don’t care bits, for the AD5663R,
AD5643R, and AD5623R, respectively (see Figure 51, Figure 52,
and Figure 53). The data bits are transferred to the DAC register
on the 24th falling edge of SCLK.
Table 8. Command Definition
C2
C1
C0
0
0
0
0
0
1
0
1
0
Command
Write to Input Register
n
Update DAC Register
n
Write to Input Register
n
, update all
(software LDAC)
Write to and update DAC Channel
n
Power down DAC (power up)
Reset
LDAC register setup
Internal reference setup (on/off)
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
Table 9. Address Command
A2
A1
0
0
0
0
0
1
0
1
1
1
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at
least 24 falling edges of SCLK, and the DAC is updated on the
24th falling edge. However, if SYNC is brought high before the
24th falling edge, this acts as an interrupt to the write sequence.
The shift register is reset, and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 54).
A0
0
1
0
1
1
ADDRESS (n)
DAC A
DAC B
Reserved
Reserved
All DACs
X
X
C2
C1
C0
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DB23 (MSB)
DB0 (LSB)
COMMAND BITS
ADDRESS BITS
DATA BITS
0
Figure 51. AD5663R Input Shift Register Contents
X
X
C2
C1
C0
A2
A1
A0
X
X
D11
D10
D13
D12
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DB23 (MSB)
DB0 (LSB)
COMMAND BITS
ADDRESS BITS
DATA BITS
0
Figure 52. AD5643R Input Shift Register Contents
X
X
C2
C1
C0
A2
A1
A0
X
X
X
X
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DB23 (MSB)
DB0 (LSB)
COMMAND BITS
ADDRESS BITS
DATA BITS
0
Figure 53. AD5623R Input Shift Register Contents
DIN
DB23
DB23
DB0
DB0
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 24
FALLING EDGE
SYNC
SCLK
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 24
FALLING EDGE
0
Figure 54. SYNC Interrupt Facility
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD5663REBZ | 功能描述:BOARD EVAL FOR AD5663 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:nanoDAC™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| EVAL-AD5664REB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad, 12-/14-/16-Bit nanoDACs with 5 ppm/C On-Chip Reference |
| EVAL-AD5664REBZ | 功能描述:BOARD EVALUATION FOR AD5664R RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:nanoDAC™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| EVAL-AD5665REBZ1 | 功能描述:BOARD EVAL FOR AD5665 TSSOP RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| EVAL-AD5665REBZ2 | 功能描述:BOARD EVAL FOR AD5665 LFCSP RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
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