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參數(shù)資料
| 型號： | EVAL-AD5453SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/28頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD5453 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 2.7M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 設(shè)置時間： | 180ns |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 125°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD5453 |
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AD5450/AD5451/AD5452/AD5453
Data Sheet
Rev. G | Page 24 of 28
MICROWIRE-to-AD5450/AD5451/AD5452/AD5453
Interface
Figure 62 shows an interface between the DAC and any
MICROWIRE-compatible device. Serial data is shifted out
upon the falling edge of the serial clock, SK, and is clocked into
the DAC input shift register upon the rising edge of SK, which
corresponds to the falling edge of the DAC’s SCLK.
SCLK
SK
MICROWIRE*
SYNC
CS
SDIN
SO
AD5450/AD5451/
AD5452/AD5453*
*ADDITIONAL PINS OMITTED FOR CLARITY
04587-106
PIC16C6x/PIC16C7x-to-
AD5450/AD5451/AD5452/AD5453 Interface
The PIC16C6x/PIC16C7x synchronous serial port (SSP) is
configured as an SPI master with the clock polarity bit (CKP) = 0.
This is done by writing to the synchronous serial port control
register (SSPCON); see the PIC16/PIC17 Microcontroller
User Manual.
In this example, I/O Port RA1 is used to provide a SYNC signal
and enable the serial port of the DAC. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, two consecutive write operations are
required. Figure 63 shows the connection diagram.
SCLK
SCK/RC3
PIC16C6x/PIC16C7x*
SYNC
RA1
SDIN
SDI/RC4
AD5450/AD5451/
AD5452/AD5453*
*ADDITIONAL PINS OMITTED FOR CLARITY
04587-
107
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which a
designed so that the analog and digital sections are separated
and confined to certain areas of the board. If the DAC is in a
system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
The star ground point should be established as close as possible
to the device.
These DACs should have ample supply bypassing of 10 F in
parallel with 0.1 F on the supply located as close to the package
as possible, ideally right up against the device. The 0.1 F
capacitor should have low effective series resistance (ESR) and
low effective series inductance (ESI), like the common ceramic
types that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching. Low ESR 1 F to 10 F tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
Components, such as clocks, that produce fast switching signals
should be shielded with a digital ground to avoid radiating noise
to other parts of the board, and they should never be run near
the reference inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A microstrip
technique is the best solution, but its use is not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to the ground plane and signal
traces are placed on the solder side.
It is good practice to employ compact, minimum lead length
PCB layout design. Leads to the input should be as short as
possible to minimize IR drops and stray inductance.
The PCB metal traces between VREF and RFB should also be
matched to minimize gain error. To optimize high frequency
performance, the I-to-V amplifier should be located as close to
the device as possible.
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