參數(shù)資料
型號(hào)： EVAL-AD5453SDZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/28頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD5453
標(biāo)準(zhǔn)包裝： 1
DAC 的數(shù)量： 1
位數(shù)： 14
采樣率（每秒）： 2.7M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
設(shè)置時(shí)間： 180ns
DAC 型： 電流
工作溫度： -40°C ~ 125°C
已供物品： 板
已用 IC / 零件： AD5453
AD5450/AD5451/AD5452/AD5453
Data Sheet
Rev. G | Page 22 of 28
04
58
7-
0
5
10
0
00
0
11
0
CONTROL BITS
DATA BITS
10
0
00
0
00
11
0
CONTROL BITS
ACTUAL DATA FRAME
INTENDED DATA FRAME
DATA BITS
Figure 55. AD5453 Second Write, Incomplete Data Sequence (0x3200) and Subsequent Additional Bits (0xF200)
Table 11.
Writing
Sequence
Data Write in
Shift Register
Action Expected
Data Transfer to
the Device
Action Carried Out
1
0x3FFF
Load and update 0x3FFF
0x3FFF
Load and update 0x3FFF
2
0x3200
Load and update 0x3200
0xF200
Clock data to shift register upon rising edge (0xF200)
MICROPROCESSOR INTERFACING
Microprocessor interfacing to a AD5450/AD5451/AD5452
/AD5453 DAC is through a serial bus that uses standard protocol
and is compatible with microcontrollers and DSP processors.
The communication channel is a 3-wire interface consisting of
a clock signal, a data signal, and a synchronization signal. The
AD5450/AD5451/AD5452/AD5453 require a 16-bit word, with
the default being data valid upon the falling edge of SCLK, but
this is changeable using the control bits in the data-word.
ADSP-21xx-to-AD5450/AD5451/AD5452/AD5453
Interface
The ADSP-21xx family of DSPs is easily interfaced to a AD5450/
AD5451/AD5452/AD5453 DAC without the need for extra glue
logic. Figure 56 is an example of an SPI interface between the DAC
and the ADSP-2191M. SCK of the DSP drives the serial data line,
SDIN. SYNC is driven from one of the port lines, in this case
SPIxSEL.
SCLK
SCK
SYNC
SPIxSEL
SDIN
MOSI
ADSP-2191M*
*ADDITIONAL PINS OMITTED FOR CLARITY
AD5450/AD5451/
AD5452/AD5453*
0
458
7-
1
00
A serial interface between the DAC and DSP SPORT is shown
in Figure 57. In this example, SPORT0 is used to transfer data to
the DAC shift register. Transmission is initiated by writing a
word to the Tx register after the SPORT has been enabled. In a
write sequence, data is clocked out upon each rising edge of the
DSP’s serial clock and clocked into the DAC input shift register
upon the falling edge of its SCLK. The update of the DAC
output takes place upon the rising edge of the SYNC signal.
SCLK
SYNC
TFS
SDIN
DT
ADSP-2101/
ADSP-2191M*
*ADDITIONAL PINS OMITTED FOR CLARITY
0
4587-
051
AD5450/AD5451/
AD5452/AD5453*
Communication between two devices at a given clock speed is
possible when the following specifications are compatible:
frame SYNC delay and frame SYNC setup-and-hold, data delay
and data setup-and-hold, and SCLK width. The DAC interface
expects a t4 (SYNC falling edge to SCLK falling edge setup time)
of 13 ns minimum. See the ADSP-21xx User Manual for infor-
mation on clock and frame SYNC frequencies for the SPORT
register. Table 12 shows the setup for the SPORT control register.
Table 12. SPORT Control Register Setup
Name
Setting
Description
TFSW
1
Alternate framing
INVTFS
1
Active low frame signal
DTYPE
00
Right justify data
ISCLK
1
Internal serial clock
TFSR
1
Frame every word
ITFS
1
Internal framing signal
SLEN
1111
16-bit data-word
ADSP-BF5xx-to-AD5450/AD5451/AD5452/AD5453
Interface
The ADSP-BF5xx family of processors has an SPI-compatible
port that enables the processor to communicate with SPI-
compatible devices. A serial interface between the BlackFin
shown in Figure 58. In this configuration, data is transferred
through the MOSI (master output, slave input) pin. SYNC is
driven by the SPIxSEL pin, which is a reconfigured
programmable flag pin.
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