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參數(shù)資料
| 型號(hào)： | EVAL-AD5453SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 16/28頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD5453 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 2.7M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 設(shè)置時(shí)間： | 180ns |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 125°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD5453 |
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Data Sheet
AD5450/AD5451/AD5452/AD5453
Rev. G | Page 23 of 28
SCLK
SCK
SYNC
SPIxSEL
SDIN
MOSI
ADSP-BF5xx*
*ADDITIONAL PINS OMITTED FOR CLARITY
AD5450/AD5451/
AD5452/AD5453*
04587-102
The ADSP-BF5xx processor incorporates channel synchronous
serial ports (SPORT). A serial interface between the DAC and
the DSP SPORT is shown in Figure 59. When the SPORT is
enabled, initiate transmission by writing a word to the Tx register.
The data is clocked out upon each rising edge of the DSP’s serial
clock and clocked into the DAC’s input shift register upon the
falling edge its SCLK. The DAC output is updated by using the
transmit frame synchronization (TFS) line to provide a SYNC
signal.
SCLK
SYNC
TFS
SDIN
DT
ADSP-BF5xx*
*ADDITIONAL PINS OMITTED FOR CLARITY
04587-103
AD5450/AD5451/
AD5452/AD5453*
80C51/80L51-to-AD5450/AD5451/AD5452/AD5453
Interface
A serial interface between the DAC and the 80C51/80L51 is
shown in Figure 60. TxD of the 80C51/80L51 drives SCLK of
the DAC serial interface, and RxD drives the serial data line,
SDIN. P1.1 is a bit-programmable pin on the serial port and is used
to drive SYNC. As data is transmitted to the switch, P1.1 is taken
low. The 80C51/80L51 transmit data only in 8-bit bytes; there-
fore, only eight falling clock edges occur in the transmit cycle.
To load data correctly to the DAC, P1.1 is left low after the first
eight bits are transmitted, and a second write cycle is initiated to
transmit the second byte of data. Data on RxD is clocked out of
the microcontroller upon the rising edge of TxD and is valid upon
the falling edge. As a result, no glue logic is required between the
DAC and microcontroller interface. P1.1 is taken high following
the completion of this cycle. The 80C51/80L51 provide the LSB
of its SBUF register as the first bit in the data stream. The DAC
input register acquires its data with the MSB as the first bit received.
The transmit routine should take this into account.
SCLK
TxD
8051*
SYNC
P1.1
SDIN
RxD
*ADDITIONAL PINS OMITTED FOR CLARITY
04587-104
AD5450/AD5451/
AD5452/AD5453*
MC68HC11-to-AD5450/AD5451/AD5452/AD5453
Interface
Figure 61 is an example of a serial interface between the DAC
and the MC68HC11 microcontroller. The serial peripheral
interface (SPI) on the MC68HC11 is configured for master
mode (MSTR) = 1, clock polarity bit (CPOL) = 0, and clock
phase bit (CPHA) = 1. The SPI is configured by writing to the
SPI control register (SPCR); see the 68HC11 User Manual. SCK
of the 68HC11 drives the SCLK of the DAC interface; the MOSI
output drives the serial data line (SDIN) of the DAC.
The SYNC signal is derived from a port line (PC7). When data
the SYNC line is taken low (PC7). Data appearing on the MOSI
output is valid upon the falling edge of SCK. Serial data from the
68HC11 is transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. Data is transmitted MSB
first. To load data to the DAC, PC7 is left low after the first eight
bits are transferred, and a second serial write operation is performed
to the DAC. PC7 is taken high at the end of this procedure.
SCLK
SCK
AD5450/AD5451/
AD5452/AD5453*
SYNC
PC7
SDIN
MOSI
MC68HC11*
*ADDITIONAL PINS OMITTED FOR CLARITY
04587-105
If the user wants to verify the data previously written to the
input shift register, the SDO line can be connected to MISO of
the MC68HC11. In this configuration with SYNC low, the shift
register clocks data out upon the rising edges of SCLK.
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