參數(shù)資料
型號(hào)： EVAL-AD5415EB
廠(chǎng)商： Analog Devices, Inc.
英文描述： Dual 12-Bit, High Bandwidth, Multiplying DAC with 4-Quadrant Resistors and Serial Interface
中文描述： 雙12位，高帶寬，乘法DAC，具有4象限電阻器和串行接口
文件頁(yè)數(shù)： 8/28頁(yè)
文件大小： 868K
代理商： EVAL-AD5415EB
AD5415
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 8 of 28
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD5415
TOP VIEW
(Not to Scale)
SDIN
SCLK
GND
V
REF
A
I
OUT
1A
I
OUT
2A
R
FB
A
R1A
R3A
R2_3A
R2A
CLR
V
DD
V
REF
B
I
OUT
1B
I
OUT
2B
R
FB
B
R1B
R3B
R2_3B
R2B
LDAC
SDO
SYNC
0
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Function
1
I
OUT
1A
2
I
OUT
2A
DAC A Current Output.
DAC A Analog Ground. This pin should normally be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
DAC Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to the external
amplifier output.
DAC A 4-Quadrant Resistors. These pins allow a number of configuration modes, including bipolar operation, with
minimum external components.
DAC A Reference Voltage Input Pin.
Ground Pin.
Load DAC Input. This pin allows asynchronous or synchronous updates to the DAC output. The DAC is
asynchronously updated when this signal goes low. Alternatively, if this line is held permanently low, an
automatic or synchronous update mode is selected whereby the DAC is updated on the 16th clock falling edge
when the device is in standalone mode or on the rising edge of SYNC when in daisy-chain mode.
Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock
input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked into
the shift register on the rising edge of SCLK.
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By
default, on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the
user to change the active edge to the rising edge.
Serial Data Output. This pin allows a number of parts to be daisy-chained. By default, data is clocked into the shift
register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the
alternate edge to loading data to the shift register. Writing the readback control word to the shift register makes
the DAC register contents available for readback on the SDO pin, clocked out on the next 16 opposite clock edges
to the active clock edge.
Active Low Control Input. The frame synchronization signal for the input data. When SYNC goes low, it powers on
the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded to the shift register on the active
edge of the following clocks. In standalone mode, the serial interface counts clocks, and data is latched to the shift
register on the 16th active clock edge.
Active Low Control Input. This pin clears the DAC output, input, and DAC registers. Configuration mode allows the
user to enable the hardware CLR pin as a clear to zero scale or midscale, as required.
Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
DAC B Reference Voltage Input Pin.
DAC B 4-Quadrant Resistors. These pins allow a number of configuration modes, including bipolar operation, with
minimum of external components.
DAC B Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to the external
amplifier output.
DAC B Analog Ground. This pin should normally be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
DAC B Current Output.
3
R
FB
A
4–7
R1A–R3A
8
9
10
V
REF
A
GND
LDAC
11
SCLK
12
SDIN
13
SDO
14
SYNC
15
CLR
16
17
18–21
V
DD
V
REF
B
R1B–R3B
22
R
FB
B
23
I
OUT
2B
24
I
OUT
1B
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-AD5415EBZ 制造商:Analog Devices 功能描述:Evaluation Board For Dual 12-Bit, High Bandwidth, Multiplying DAC With 4-Quadrant Resistors And Serial Interface 制造商:Analog Devices 功能描述:DUAL 12-BIT, HIGH BANDWIDTH, MULTIPLYING DAC W/ 4-QUADRANT R - Bulk
EVAL-AD5415SDZ 功能描述:BOARD EVAL FOR AD5415 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
EVAL-AD5420EBZ 功能描述:BOARD EVALUATION FOR AD5420 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
EVAL-AD5421SDZ 功能描述:BOARD EVAL FOR AD5421 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
EVAL-AD5422EBZ 功能描述:BOARD EVAL FOR AD5422 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
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