- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362800 > EVAL-AD5415EB (Analog Devices, Inc.) Dual 12-Bit, High Bandwidth, Multiplying DAC with 4-Quadrant Resistors and Serial Interface PDF資料下載
參數(shù)資料
| 型號： | EVAL-AD5415EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual 12-Bit, High Bandwidth, Multiplying DAC with 4-Quadrant Resistors and Serial Interface |
| 中文描述： | 雙12位，高帶寬，乘法DAC，具有4象限電阻器和串行接口 |
| 文件頁數(shù)： | 20/28頁 |
| 文件大?。?/td> | 868K |
| 代理商： | EVAL-AD5415EB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
AD5415
SERIAL INTERFACE
The AD5415 has an easy-to-use 3-wire interface, which is
compatible with SPI, QSPI, MICROWIRE, and DSP interface
standards. Data is written to the device in 16-bit words. Each
16-bit word consists of four control bits and 12 data bits, as
shown in Figure 39.
Rev. 0 | Page 20 of 28
LOW POWER SERIAL INTERFACE
To minimize the power consumption of the device, the interface
powers up fully only when the device is being written to, that is,
on the falling edge of SYNC. The SCLK and DIN input buffers
are powered down on the rising edge of SYNC.
DAC Control Bits C3 to C0
Control bits C3 to C0 allow control of various functions of the
DAC, as shown in Table 11. Default settings of the DAC at
power-on are as follows. Data is clocked into the shift register
on falling clock edges; daisy-chain mode is enabled. The device
powers on with zero-scale load to the DAC register and I
OUT
lines. The DAC control bits allow the user to adjust certain
features at power-on. For example, daisy-chaining can be
disabled when not in use, active clock edge can be changed to
rising edge, and DAC output can be cleared to either zero scale
or midscale. The user can also initiate a readback of the DAC
register contents for verification purposes.
CONTROL REGISTER
(Control Bits = 1101)
While maintaining software compatibility with the single-
channel current output DACs (AD5426/AD5433/AD5443), this
DAC also features some additional interface functionality.
Simply set the control bits to 1101 to enter control register
mode. Figure 40 shows the contents of the control register, the
functions of which are described in the following sections.
SDO Control (SDO1 and SDO2)
The SDO bits enable the user to control the SDO output driver
strength, disable the SDO output, or configure it as an open-
drain driver. The strength of the SDO driver affects the timing
of t
12
and, when stronger, allows a faster clock cycle to be used.
Table 10. SDO Control Bits
SDO2
SDO1
Function
0
0
Full SDO Driver
0
1
SDO Configured as Open Drain
1
0
Weak SDO Driver
1
1
Disable SDO Output
Daisy-Chain Control (DSY)
DSY enables or disables daisy-chain mode. A 1 enables daisy-
chain mode; a 0 disables it. When disabled, a readback request is
accepted, SDO is automatically enabled, the DAC register
contents of the relevant DAC are clocked out on SDO, and,
when complete, SDO is disabled again.
Hardware CLR Bit (HCLR)
The default setting for the hardware CLR pin is to clear the
registers and DAC output to zero code. A 1 in the HCLR bit
clears the DAC outputs to midscale; a 0 clears them to
zero scale.
Active Clock Edge (SCLK)
The default active clock edge is the falling edge. Write a 1 to this
bit to clock data in on the rising edge; write a 0 to clock it on the
falling edge.
DATA BITS
CONTROL BITS
C3
C2
C1
C0
DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB0 (LSB)
DB15 (MSB)
0
Figure 39. AD5415 12-Bit Input Shift Register Contents
CONTROL BITS
1
1
0
1
SDO1 SDO2
DSY
HCLR SCLK
X
X
X
X
X
X
X
DB0 (LSB)
DB15 (MSB)
0
Figure 40. Control Register Loading Sequence
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EVAL-AD5426EB | 8-/10-/12-Bit High Bandwidth Multiplying DACs with Serial Interface |
| EVAL-AD5432EB | CAP, .22UF, 10V, SMT, 0603 |
| EVAL-AD5443EB | CAP X7R 470PF 50V 10% 0603 |
| EVAL-AD5520EB | Per Pin Parametric Measurement Unit/Source Measure Unit |
| EVAL-AD5532EB | 32-Channel, 14-Bit Voltage-Output DAC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD5415EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For Dual 12-Bit, High Bandwidth, Multiplying DAC With 4-Quadrant Resistors And Serial Interface 制造商:Analog Devices 功能描述:DUAL 12-BIT, HIGH BANDWIDTH, MULTIPLYING DAC W/ 4-QUADRANT R - Bulk |
| EVAL-AD5415SDZ | 功能描述:BOARD EVAL FOR AD5415 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| EVAL-AD5420EBZ | 功能描述:BOARD EVALUATION FOR AD5420 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| EVAL-AD5421SDZ | 功能描述:BOARD EVAL FOR AD5421 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| EVAL-AD5422EBZ | 功能描述:BOARD EVAL FOR AD5422 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。