參數(shù)資料
型號: EVAL-AD5415EB
廠商: Analog Devices, Inc.
英文描述: Dual 12-Bit, High Bandwidth, Multiplying DAC with 4-Quadrant Resistors and Serial Interface
中文描述: 雙12位,高帶寬,乘法DAC,具有4象限電阻器和串行接口
文件頁數(shù): 16/28頁
文件大?。?/td> 868K
代理商: EVAL-AD5415EB
AD5415
BIPOLAR OPERATION
In some applications, it might be necessary to generate full
4-quadrant multiplying operation or a bipolar output swing.
This can be easily accomplished by using another external
amplifier and the on chip 4-quadrant resistors, as shown in
Figure 34.
Rev. 0 | Page 16 of 28
When in bipolar mode, the output voltage is given by
V
OUT
=
V
REF
×
D
/2
n
1
V
REF
where
D
is the fractional representation of the digital word
loaded to the DAC, in the range of 0 to 4095.
n
is the number of bits.
When V
IN
is an ac signal, the circuit performs 4-quadrant
multiplication.
Table 6 shows the relationship between digital code and the
expected output voltage for bipolar operation.
Table 6. Bipolar Code Table
Digital Input
1111 1111
1000 0000
0000 0001
0000 0000
Analog Output (V)
+V
REF
(2047/2048)
0
V
REF
(2047/2048)
V
REF
(2048/2048)
STABILITY
In the I-to-V configuration, the I
OUT
of the DAC and the
inverting node of the op amp must be connected as close as
possible, and proper PCB layout techniques must be employed.
Because every code change corresponds to a step function, gain
peaking can occur if the op amp has limited GBP and there is
excessive parasitic capacitance at the inverting node. This
parasitic capacitance introduces a pole into the open loop
response that can cause ringing or instability in the closed loop
application’s circuit.
An optional compensation capacitor, C1, can be added in
parallel with R
FB
for stability, as shown in Figure 33 and
Figure 34. Too small a value of C1 can produce ringing at the
output, while too large a value can adversely affect the settling
time. C1 should be found empirically, but 1 pF to 2 pF is
generally adequate for the compensation.
I
OUT
1A
I
OUT
2A
R
FB
A
R
FB
2R
R1
2R
AD5415
12-BIT DAC A
R
GND
SDIN
V
REF
A
SCLK
SYNC
R2
2R
R3
2R
R2A
R2_3A
R3A
V
DD
C1
A1
V
OUT
= –V
IN
TO +V
IN
A1
AGND
uCONTROLLER
R1A
AGND
AGND
V
IN
NOTES:
1
DAC B OMITTED FOR CLARITY.
2
C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED,
IF A1 IS A HIGH SPEED AMPLIFIER.
0
Figure 34. Bipolar Operation
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