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參數(shù)資料
| 型號(hào)： | EVAL-AD421EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Loop-Powered 4 mA to 20 mA DAC |
| 中文描述： | 回路供電4毫安到20毫安援 |
| 文件頁(yè)數(shù)： | 9/14頁(yè) |
| 文件大?。?/td> | 171K |
| 代理商： | EVAL-AD421EB |
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AD421
–
9
–
REV. C
The HC11 generates the requisite eight clock pulses with data
valid on the rising edges. After the MSBY is transmitted, the
least significant byte (LSBY) is loaded from memory and
transmitted in a similar fashion. To complete the transfer, the
LATCH pin is driven high when loading the complete 16-bit
word into the AD421.
AD421 TO MICROWIRE INTERFACE
The flexible serial interface of the AD421 is also compatible
with the National Semiconductor MICROWIRE interface. The
MICROWIRE interface is used in microcontrollers such as the
COP400 and COP800 series of processors. A generic interface
to use the MICROWIRE interface is shown in Figure 9. The
G1, SK, and SO pins of the MICROWIRE interface respec-
tively connect to the LATCH, CLOCK, and DATA IN pins of
the AD421.
SK
SO
CLOCK
DATA IN
LATCH
AD421*
MICROWIRE
* ADDITIONAL PINS OMITTED FOR CLARITY
Figure 9. AD421 to MICROWIRE Interface
G1
Opto-Isolated Interface
The AD421 has a versatile serial 3-wire serial interface making
it ideal for minimizing the number of control lines required for
isolation of the digital system from the control loop. In intrinsi-
cally safe applications or due to noise, safety requirements, or
distance, it may be necessary to isolate the AD421 from the
controller. This can easily be achieved by using opto-isolators.
Figure 10 shows an opto-isolated interface to the AD421 where
CLOCK, DATAIN and LATCH are driven from opto-couplers.
Be aware of signal inversion across the opto-couplers. If opto-
couplers with relatively slow rise and fall times are used, Schmitt
triggers may be required on the digital inputs to prevent errone-
ous data being presented to the DAC.
0.1 F
2.2 F
V
CC
10k
V
CC
10k
V
CC
10k
V
CC
CLOCK
LATCH
DATA IN
AD421*
COM
CLOCK
LATCH
DATA IN
V
CC
* ADDITIONAL PINS OMITTED FOR CLARITY
Figure 10. Opto-Isolated Interface
APPLICATIONS SECTION
Basic Operating Configuration
Figure 11 shows the basic connection diagram for the AD421
operating at 5 V. This circuit shows the minimum of external
components to operate the AD421. In the diagram, the AD421’s
regulator loop in conjunction with the DN25D pass transistor
provides the V
CC
voltage for the AD421 itself and for other
devices in the transmitter. The V
CC
pin should be well decou-
pled with a 2.2
μ
F capacitor to ensure regulator stability and to
absorb power glitches on the V
CC
line of the AD421 and other
devices in the system. If the AD421 is operated with V
CC
= 3 V,
the transfer function shifts negative. To correct for this a 16k
resistor connected between COM and LOOPRTN will approxi-
mately compensate for the V
CC
supply sensitivity in moving from
5 V to 3 V by adjusting the gain of the AD421.
C1
C2
C3
COM
COM TO EXTERNAL
CIRCUITRY
V
CC
LV
2.2 F
COM
V
CC
TO EXTERNAL
CIRCUITRY
DN25D
DRIVE
COMP
0.01 F
1k
1000pF
BOOST
LOOP RTN
V
LOOP
0.01 F
0.01 F
0.0033 F
LATCH
CLOCK
DATA
REF IN
REF OUT2
REF OUT1
4.7 F
COM
AD421
Figure 11. Basic Connection Diagram
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